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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Aurelien Jarno" <aurelien@aurel32.net>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 17/27] target/mips: Introduce mxu_translate_init() helper
Date: Sat, 13 Mar 2021 20:48:19 +0100	[thread overview]
Message-ID: <20210313194829.2193621-18-f4bug@amsat.org> (raw)
In-Reply-To: <20210313194829.2193621-1-f4bug@amsat.org>

Extract the MXU register initialization code from mips_tcg_init()
as a new mxu_translate_init() helper. Make it public and replace
!TARGET_MIPS64 ifdef'ry by the 'TARGET_LONG_BITS == 32' check to
elide this code at preprocessing time.

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
---
 target/mips/translate.h |  1 +
 target/mips/translate.c | 28 ++++++++++++++++------------
 2 files changed, 17 insertions(+), 12 deletions(-)

diff --git a/target/mips/translate.h b/target/mips/translate.h
index a5c49f1ee22..a807b3d2566 100644
--- a/target/mips/translate.h
+++ b/target/mips/translate.h
@@ -179,6 +179,7 @@ extern TCGv bcond;
 void msa_translate_init(void);
 
 /* MXU */
+void mxu_translate_init(void);
 bool decode_ase_mxu(DisasContext *ctx, uint32_t insn);
 
 /* decodetree generated */
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2139109744f..a1a9a850085 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2045,7 +2045,20 @@ static const char * const mxuregnames[] = {
     "XR1",  "XR2",  "XR3",  "XR4",  "XR5",  "XR6",  "XR7",  "XR8",
     "XR9",  "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR",
 };
-#endif
+
+void mxu_translate_init(void)
+{
+    for (unsigned i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
+        mxu_gpr[i] = tcg_global_mem_new(cpu_env,
+                                        offsetof(CPUMIPSState, active_tc.mxu_gpr[i]),
+                                        mxuregnames[i]);
+    }
+
+    mxu_CR = tcg_global_mem_new(cpu_env,
+                                offsetof(CPUMIPSState, active_tc.mxu_cr),
+                                mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
+}
+#endif /* !TARGET_MIPS64 */
 
 /* General purpose registers moves. */
 void gen_load_gpr(TCGv t, int reg)
@@ -28047,18 +28060,9 @@ void mips_tcg_init(void)
     cpu_llval = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, llval),
                                    "llval");
 
-#if !defined(TARGET_MIPS64)
-    for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) {
-        mxu_gpr[i] = tcg_global_mem_new(cpu_env,
-                                        offsetof(CPUMIPSState,
-                                                 active_tc.mxu_gpr[i]),
-                                        mxuregnames[i]);
+    if (TARGET_LONG_BITS == 32) {
+        mxu_translate_init();
     }
-
-    mxu_CR = tcg_global_mem_new(cpu_env,
-                                offsetof(CPUMIPSState, active_tc.mxu_cr),
-                                mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]);
-#endif /* !TARGET_MIPS64 */
 }
 
 void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb,
-- 
2.26.2



  parent reply	other threads:[~2021-03-13 19:59 UTC|newest]

Thread overview: 31+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-13 19:48 [PULL 00/27] MIPS patches for 2021-03-13 Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 01/27] hw/mips/gt64xxx: Initialize ISD I/O memory region in DeviceRealize() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 02/27] hw/mips/gt64xxx: Simplify ISD MemoryRegion read/write handlers Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 03/27] hw/mips/gt64xxx: Fix typos in qemu_log_mask() formats Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 04/27] hw/mips/gt64xxx: Rename trace events related to interrupt registers Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 05/27] hw/mips/gt64xxx: Trace accesses to ISD registers Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 06/27] target/mips/meson: Introduce mips_tcg source set Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 07/27] target/mips/meson: Restrict mips-semi.c to TCG Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 08/27] target/mips: Rewrite complex ifdef'ry Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 09/27] target/mips: Remove XBurst Media eXtension Unit dead code Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 10/27] target/mips: Remove unused CPUMIPSState* from MXU functions Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 11/27] target/mips: Pass instruction opcode to decode_opc_mxu() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 12/27] target/mips: Use OPC_MUL instead of OPC__MXU_MUL Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 13/27] target/mips: Move MUL opcode check from decode_mxu() to decode_legacy() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 14/27] target/mips: Rename decode_opc_mxu() as decode_ase_mxu() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 15/27] target/mips: Convert decode_ase_mxu() to decodetree prototype Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 16/27] target/mips: Simplify decode_opc_mxu() ifdef'ry Philippe Mathieu-Daudé
2021-03-13 19:48 ` Philippe Mathieu-Daudé [this message]
2021-03-13 19:48 ` [PULL 18/27] target/mips: Extract MXU code to new mxu_translate.c file Philippe Mathieu-Daudé
2021-03-15 21:33   ` Peter Maydell
2021-03-15 22:43     ` Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 19/27] target/mips: Use gen_load_gpr[_hi]() when possible Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 20/27] target/mips/tx79: Move MFHI1 / MFLO1 opcodes to decodetree Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 21/27] target/mips/tx79: Move MTHI1 / MTLO1 " Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 22/27] target/mips/translate: Make gen_rdhwr() public Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 23/27] target/mips/translate: Simplify PCPYH using deposit_i64() Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 24/27] target/mips/tx79: Move PCPYH opcode to decodetree Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 25/27] target/mips/tx79: Move PCPYLD / PCPYUD opcodes " Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 26/27] target/mips: Remove 'C790 Multimedia Instructions' dead code Philippe Mathieu-Daudé
2021-03-13 19:48 ` [PULL 27/27] target/mips/tx79: Salvage instructions description comment Philippe Mathieu-Daudé
2021-03-15 15:34 ` [PULL 00/27] MIPS patches for 2021-03-13 Peter Maydell

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