From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1F89EC433DB for ; Fri, 26 Mar 2021 20:28:23 +0000 (UTC) Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C586F619FC for ; Fri, 26 Mar 2021 20:28:22 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C586F619FC Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=suse.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Received: from localhost ([::1]:48956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1lPt49-0007R1-MZ for qemu-devel@archiver.kernel.org; Fri, 26 Mar 2021 16:28:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPsHt-0007Te-5d for qemu-devel@nongnu.org; Fri, 26 Mar 2021 15:38:29 -0400 Received: from mx2.suse.de ([195.135.220.15]:46306) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1lPsHp-0001OA-CU for qemu-devel@nongnu.org; Fri, 26 Mar 2021 15:38:28 -0400 X-Virus-Scanned: by amavisd-new at test-mx.suse.de Received: from relay2.suse.de (unknown [195.135.221.27]) by mx2.suse.de (Postfix) with ESMTP id 35CE8AF2A; Fri, 26 Mar 2021 19:38:14 +0000 (UTC) From: Claudio Fontana To: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Alex=20Benn=C3=A9e?= Subject: [RFC v12 61/65] cpu-sve: rename sve_zcr_len_for_el to cpu_sve_get_zcr_len_for_el Date: Fri, 26 Mar 2021 20:36:57 +0100 Message-Id: <20210326193701.5981-62-cfontana@suse.de> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210326193701.5981-1-cfontana@suse.de> References: <20210326193701.5981-1-cfontana@suse.de> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=195.135.220.15; envelope-from=cfontana@suse.de; helo=mx2.suse.de X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Roman Bolshakov , Claudio Fontana , Eduardo Habkost , qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" use a canonical module prefix followed by the get_zcr_len_for_el() method name. Also rename the static internal auxiliary function, where the module prefix is not necessary. Signed-off-by: Claudio Fontana --- target/arm/cpu-sve.h | 2 +- target/arm/arch_dump.c | 2 +- target/arm/cpu-sve.c | 6 +++--- target/arm/cpu64.c | 2 +- target/arm/tcg/cpregs.c | 4 ++-- target/arm/tcg/helper.c | 4 ++-- target/arm/tcg/tcg-sve.c | 4 ++-- 7 files changed, 12 insertions(+), 12 deletions(-) diff --git a/target/arm/cpu-sve.h b/target/arm/cpu-sve.h index 1512c56a6b..c83508ea0a 100644 --- a/target/arm/cpu-sve.h +++ b/target/arm/cpu-sve.h @@ -35,6 +35,6 @@ void cpu_sve_add_props(Object *obj); void cpu_sve_add_props_max(Object *obj); /* return the vector length for EL */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el); +uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el); #endif /* CPU_SVE_H */ diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 11509557e3..dce55065ac 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -169,7 +169,7 @@ static off_t sve_fpcr_offset(uint32_t vq) static uint32_t sve_current_vq(CPUARMState *env) { - return sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + return cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + 1; } static size_t sve_size_vq(uint32_t vq) diff --git a/target/arm/cpu-sve.c b/target/arm/cpu-sve.c index e8e817e110..1bc8c0bdb0 100644 --- a/target/arm/cpu-sve.c +++ b/target/arm/cpu-sve.c @@ -289,7 +289,7 @@ void cpu_sve_add_props_max(Object *obj) object_property_add(obj, "sve-max-vq", "uint32", get_prop_max_vq, set_prop_max_vq, NULL, NULL); } -static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) +static uint32_t get_valid_len(ARMCPU *cpu, uint32_t start_len) { uint32_t end_len; @@ -304,7 +304,7 @@ static uint32_t sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) /* * Given that SVE is enabled, return the vector length for EL. */ -uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) +uint32_t cpu_sve_get_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu = env_archcpu(env); uint32_t zcr_len = cpu->sve_max_vq - 1; @@ -319,5 +319,5 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) zcr_len = MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } - return sve_zcr_get_valid_len(cpu, zcr_len); + return get_valid_len(cpu, zcr_len); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b1d63fb7a7..c30ecd1de4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -505,7 +505,7 @@ static void aarch64_cpu_dump_state(CPUState *cs, FILE *f, int flags) vfp_get_fpcr(env), vfp_get_fpsr(env)); if (cpu_isar_feature(aa64_sve, cpu) && sve_exception_el(env, el) == 0) { - int j, zcr_len = sve_zcr_len_for_el(env, el); + int j, zcr_len = cpu_sve_get_zcr_len_for_el(env, el); for (i = 0; i <= FFR_PRED_NUM; i++) { bool eol; diff --git a/target/arm/tcg/cpregs.c b/target/arm/tcg/cpregs.c index 4c7d96f465..dd005a1655 100644 --- a/target/arm/tcg/cpregs.c +++ b/target/arm/tcg/cpregs.c @@ -5803,7 +5803,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { int cur_el = arm_current_el(env); - int old_len = sve_zcr_len_for_el(env, cur_el); + int old_len = cpu_sve_get_zcr_len_for_el(env, cur_el); int new_len; /* Bits other than [3:0] are RAZ/WI. */ @@ -5814,7 +5814,7 @@ static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, * Because we arrived here, we know both FP and SVE are enabled; * otherwise we would have trapped access to the ZCR_ELn register. */ - new_len = sve_zcr_len_for_el(env, cur_el); + new_len = cpu_sve_get_zcr_len_for_el(env, cur_el); if (new_len < old_len) { tcg_sve_narrow_vq(env, new_len + 1); } diff --git a/target/arm/tcg/helper.c b/target/arm/tcg/helper.c index b157b3615c..e8d6cdf2db 100644 --- a/target/arm/tcg/helper.c +++ b/target/arm/tcg/helper.c @@ -187,7 +187,7 @@ static int arm_gdb_get_svereg(CPUARMState *env, GByteArray *buf, int reg) * We report in Vector Granules (VG) which is 64bit in a Z reg * while the ZCR works in Vector Quads (VQ) which is 128bit chunks. */ - int vq = sve_zcr_len_for_el(env, arm_current_el(env)) + 1; + int vq = cpu_sve_get_zcr_len_for_el(env, arm_current_el(env)) + 1; return gdb_get_reg64(buf, vq * 2); } default: @@ -1120,7 +1120,7 @@ static uint32_t rebuild_hflags_a64(CPUARMState *env, int el, int fp_el, if (sve_el != 0 && fp_el == 0) { zcr_len = 0; } else { - zcr_len = sve_zcr_len_for_el(env, el); + zcr_len = cpu_sve_get_zcr_len_for_el(env, el); } flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el); flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len); diff --git a/target/arm/tcg/tcg-sve.c b/target/arm/tcg/tcg-sve.c index 25d5a5867c..80a37caf6e 100644 --- a/target/arm/tcg/tcg-sve.c +++ b/target/arm/tcg/tcg-sve.c @@ -155,10 +155,10 @@ void tcg_sve_change_el(CPUARMState *env, int old_el, */ old_a64 = old_el ? arm_el_is_aa64(env, old_el) : el0_a64; old_len = (old_a64 && !sve_exception_el(env, old_el) - ? sve_zcr_len_for_el(env, old_el) : 0); + ? cpu_sve_get_zcr_len_for_el(env, old_el) : 0); new_a64 = new_el ? arm_el_is_aa64(env, new_el) : el0_a64; new_len = (new_a64 && !sve_exception_el(env, new_el) - ? sve_zcr_len_for_el(env, new_el) : 0); + ? cpu_sve_get_zcr_len_for_el(env, new_el) : 0); /* When changing vector length, clear inaccessible state. */ if (new_len < old_len) { -- 2.26.2