From: matheus.ferst@eldorado.org.br
To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org
Cc: richard.henderson@linaro.org, f4bug@amsat.org,
luis.pires@eldorado.org.br, lagarcia@br.ibm.com,
bruno.larsen@eldorado.org.br, matheus.ferst@eldorado.org.br,
david@gibson.dropbear.id.au
Subject: [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions
Date: Mon, 17 May 2021 17:50:02 -0300 [thread overview]
Message-ID: <20210517205025.3777947-1-matheus.ferst@eldorado.org.br> (raw)
From: Matheus Ferst <matheus.ferst@eldorado.org.br>
This series provides the basic infrastructure for adding the new 32/64-bit
instructions in Power ISA 3.1 to target/ppc.
v5:
- Rebase on ppc-for-6.1;
- Change copyright line from new files;
- Remove argument set from PNOP;
- Add comments to explain helper_cfuged implementation;
- New REQUIRE_ALTIVEC macro;
- REQUIRE_ALTIVEC and REQUIRE_INSNS_FLAGS2 in trans_CFUGED;
- cmp/cmpi/cmpl/cmpli moved to decodetree.
v4:
- Rebase on ppc-for-6.1;
- Fold do_ldst_D and do_ldst_X;
- Add tcg_const_tl, used to share do_ldst_D and do_ldst_X code;
- Unfold prefixed and non-prefixed loads/stores/addi to let non-prefixed insns use the non-prefixed formats;
- PNOP invalid suffixes;
- setbc/setbcr/stnbc/setnbcr implemented;
- cfuged/vcfuged implemented;
- addpcis moved to decodetree.
v3:
- More changes for decodetree.
- Cleanup exception/is_jmp logic to the point exception is removed.
- Fold in Luis' isa check for prefixed insn support.
- Share trans_* between prefixed and non-prefixed instructions.
- Use macros to minimize the trans_* boilerplate.
- Fix decode mistake for STHX/STHXU.
v2:
- Store current pc in ctx instead of insn_size
- Use separate decode files for 32- and 64-bit instructions
- Improvements to the exception/is_jmp logic
- Use translator_loop_temp_check()
- Moved logic to prevent translation from crossing page boundaries
- Additional instructions using decodetree: addis, pnop, loads/stores
- Added check for prefixed insn support in cpu flags
Matheus Ferst (6):
TCG: add tcg_constant_tl
target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions
target/ppc: Implement cfuged instruction
target/ppc: Implement vcfuged instruction
target/ppc: Move addpcis to decodetree
target/ppc: Move cmp/cmpi/cmpl/cmpli to decodetree
Richard Henderson (17):
target/ppc: Introduce gen_icount_io_start
target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE
target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN
target/ppc: Remove DisasContext.exception
target/ppc: Move single-step check to ppc_tr_tb_stop
target/ppc: Tidy exception vs exit_tb
target/ppc: Mark helper_raise_exception* as noreturn
target/ppc: Use translator_loop_temp_check
target/ppc: Introduce macros to check isa extensions
target/ppc: Move page crossing check to ppc_tr_translate_insn
target/ppc: Add infrastructure for prefixed insns
target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI
target/ppc: Implement PNOP
target/ppc: Move D/DS/X-form integer loads to decodetree
target/ppc: Implement prefixed integer load instructions
target/ppc: Move D/DS/X-form integer stores to decodetree
target/ppc: Implement prefixed integer store instructions
include/tcg/tcg-op.h | 2 +
linux-user/ppc/cpu_loop.c | 6 -
target/ppc/cpu.h | 4 +-
target/ppc/helper.h | 5 +-
target/ppc/insn32.decode | 126 ++++
target/ppc/insn64.decode | 124 ++++
target/ppc/int_helper.c | 62 ++
target/ppc/meson.build | 9 +
target/ppc/translate.c | 659 +++++----------------
target/ppc/translate/fixedpoint-impl.c.inc | 279 +++++++++
target/ppc/translate/vector-impl.c.inc | 56 ++
11 files changed, 820 insertions(+), 512 deletions(-)
create mode 100644 target/ppc/insn32.decode
create mode 100644 target/ppc/insn64.decode
create mode 100644 target/ppc/translate/fixedpoint-impl.c.inc
create mode 100644 target/ppc/translate/vector-impl.c.inc
--
2.25.1
next reply other threads:[~2021-05-17 20:54 UTC|newest]
Thread overview: 57+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-17 20:50 matheus.ferst [this message]
2021-05-17 20:50 ` [PATCH v5 01/23] target/ppc: Introduce gen_icount_io_start matheus.ferst
2021-05-18 0:13 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 02/23] target/ppc: Replace POWERPC_EXCP_STOP with DISAS_EXIT_UPDATE matheus.ferst
2021-05-18 0:14 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 03/23] target/ppc: Replace POWERPC_EXCP_BRANCH with DISAS_NORETURN matheus.ferst
2021-05-18 0:15 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 04/23] target/ppc: Remove DisasContext.exception matheus.ferst
2021-05-18 0:17 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 05/23] target/ppc: Move single-step check to ppc_tr_tb_stop matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 06/23] target/ppc: Tidy exception vs exit_tb matheus.ferst
2021-05-18 0:19 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 07/23] target/ppc: Mark helper_raise_exception* as noreturn matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 08/23] target/ppc: Use translator_loop_temp_check matheus.ferst
2021-05-18 0:20 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 09/23] target/ppc: Introduce macros to check isa extensions matheus.ferst
2021-05-18 0:21 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 10/23] target/ppc: Move page crossing check to ppc_tr_translate_insn matheus.ferst
2021-05-18 0:23 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 11/23] target/ppc: Add infrastructure for prefixed insns matheus.ferst
2021-05-18 0:25 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 12/23] target/ppc: Move ADDI, ADDIS to decodetree, implement PADDI matheus.ferst
2021-05-18 0:35 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 13/23] target/ppc: Implement PNOP matheus.ferst
2021-05-18 0:36 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 14/23] TCG: add tcg_constant_tl matheus.ferst
2021-05-18 0:37 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 15/23] target/ppc: Move D/DS/X-form integer loads to decodetree matheus.ferst
2021-05-18 0:44 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 16/23] target/ppc: Implement prefixed integer load instructions matheus.ferst
2021-05-18 0:45 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 17/23] target/ppc: Move D/DS/X-form integer stores to decodetree matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 18/23] target/ppc: Implement prefixed integer store instructions matheus.ferst
2021-05-18 0:47 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 19/23] target/ppc: Implement setbc/setbcr/stnbc/setnbcr instructions matheus.ferst
2021-05-18 0:49 ` David Gibson
2021-05-18 9:48 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 20/23] target/ppc: Implement cfuged instruction matheus.ferst
2021-05-18 0:51 ` David Gibson
2021-05-17 20:50 ` [PATCH v5 21/23] target/ppc: Implement vcfuged instruction matheus.ferst
2021-05-18 0:52 ` David Gibson
2021-05-18 9:54 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 22/23] target/ppc: Move addpcis to decodetree matheus.ferst
2021-05-18 0:53 ` David Gibson
2021-05-18 9:55 ` Richard Henderson
2021-05-17 20:50 ` [PATCH v5 23/23] target/ppc: Move cmp/cmpi/cmpl/cmpli " matheus.ferst
2021-05-18 0:56 ` David Gibson
2021-05-18 10:12 ` Richard Henderson
2021-05-21 17:25 ` Matheus K. Ferst
2021-05-24 18:51 ` Richard Henderson
2021-05-26 15:17 ` Matheus K. Ferst
2021-05-26 16:11 ` Richard Henderson
2021-05-27 1:11 ` David Gibson
2021-05-18 3:58 ` [PATCH v5 00/23] Base for adding PowerPC 64-bit instructions David Gibson
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