From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8CAFC433ED for ; Thu, 20 May 2021 14:03:58 +0000 (UTC) Received: from desiato.infradead.org (desiato.infradead.org [90.155.92.199]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 45B166109F for ; Thu, 20 May 2021 14:03:58 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 45B166109F Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=desiato.20200630; h=Sender:Content-Transfer-Encoding :Content-Type:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:Cc:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=L+Mk/gk/C3AWQYTOMFLd59d5eWuMNUYLrdY8lmKx790=; b=ppfeEmy6LQ4f9UmVqJDC4zyD7a TwYnNTUFL/1uRvqRXe192DEyGGhM/7s0+j2SB6eAbYz9o7Ub2BcED4EUujJh7SNUl0P2lgcsOwbLl M9zaNqwYlXwmHrry4co+/XXhBUIGMRSlZaqCbtHh2Abl4yX4dpA3HocGaTJRIBtQxmtVDkVecPpNf nn69VUxVlc75SZlncIKj702+Mh/SV3T8OdBwAVvcwudDDpUP/gf+SciX2Mx99x9MF8PoEznCl9BL3 xdCPv8GR14b40d02s04bsAGzL8G96dflW10L3nA1Rfpzp5ADDjA/AT7KCXCb4APG5y/AFvyomLpvc tzyjJjzg==; Received: from localhost ([::1] helo=desiato.infradead.org) by desiato.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ljjFs-001L6W-5P; Thu, 20 May 2021 14:02:28 +0000 Received: from bombadil.infradead.org ([2607:7c80:54:e::133]) by desiato.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1ljjFq-001L61-8h for linux-arm-kernel@desiato.infradead.org; Thu, 20 May 2021 14:02:26 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=bombadil.20210309; h=In-Reply-To:Content-Type:MIME-Version :References:Message-ID:Subject:Cc:To:From:Date:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description; bh=wwr1sWiFnhka33KxJlDcDXshz9FhwA6qdOmRABRSLUY=; b=LybLarmtL1zC6gmGJx6rP2e1S7 5dSRBHuPGMT78cS+7G34nfQQl4GMHvP3zf2vdux9Ohs6Hv3XTj/dzI8IrWxea94HtKmhkWuOqL6Dp f4nkbqdG7N1MH5tutunZuzp8OdOSDiCICzjtNIOXppX4o//M76A1Xf7CinWkYSdZCzy0gC7kS3ol2 yYqncbn0C9geZ5EUmCpxqNwV/kQ6sSMQngSwnbsc2ZWp2SR7iYRZMngK99Fe1qMgK2FnYh1FCnRkJ i3nVyNwNZ0ibC1uSmZudOjVkzkITTh9LfVZvF9NcmxJXe7yAZeOvhn3iVA5N3z9I1OXsHJADgxI1V zefkUWUw==; Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94 #2 (Red Hat Linux)) id 1ljjFn-00GOvU-3N for linux-arm-kernel@lists.infradead.org; Thu, 20 May 2021 14:02:25 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 57B6611D4; Thu, 20 May 2021 07:02:21 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.7.235]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 854E53F73B; Thu, 20 May 2021 07:02:19 -0700 (PDT) Date: Thu, 20 May 2021 15:02:16 +0100 From: Mark Rutland To: Fuad Tabba Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org, catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org, james.morse@arm.com, alexandru.elisei@arm.com, suzuki.poulose@arm.com, robin.murphy@arm.com Subject: Re: [PATCH v3 05/18] arm64: Do not enable uaccess for flush_icache_range Message-ID: <20210520140216.GG17233@C02TD0UTHF1T.local> References: <20210520124406.2731873-1-tabba@google.com> <20210520124406.2731873-6-tabba@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210520124406.2731873-6-tabba@google.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210520_070223_257273_7FC18D8F X-CRM114-Status: GOOD ( 24.71 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, May 20, 2021 at 01:43:53PM +0100, Fuad Tabba wrote: > __flush_icache_range works on the kernel linear map, and doesn't > need uaccess. The existing code is a side-effect of its current > implementation with __flush_cache_user_range fallthrough. > > Instead of fallthrough to share the code, use a common macro for > the two where the caller specifies an optional fixup label if > user access is needed. If provided, this label would be used to > generate an extable entry. > > No functional change intended. > Possible performance impact due to the reduced number of > instructions. > > Reported-by: Catalin Marinas > Reported-by: Will Deacon > Link: https://lore.kernel.org/linux-arch/20200511110014.lb9PEahJ4hVOYrbwIb_qUHXyNy9KQzNFdb_I3YlzY6A@z/ > Signed-off-by: Fuad Tabba I have one comment below, but either way this looks good to me, so: Acked-by: Mark Rutland > --- > arch/arm64/mm/cache.S | 64 +++++++++++++++++++++++++++---------------- > 1 file changed, 41 insertions(+), 23 deletions(-) > > diff --git a/arch/arm64/mm/cache.S b/arch/arm64/mm/cache.S > index 5ff8dfa86975..c6bc3b8138e1 100644 > --- a/arch/arm64/mm/cache.S > +++ b/arch/arm64/mm/cache.S > @@ -14,6 +14,41 @@ > #include > #include > > +/* > + * __flush_cache_range(start,end) [fixup] > + * > + * Ensure that the I and D caches are coherent within specified region. > + * This is typically used when code has been written to a memory region, > + * and will be executed. > + * > + * - start - virtual start address of region > + * - end - virtual end address of region > + * - fixup - optional label to branch to on user fault > + */ > +.macro __flush_cache_range, fixup > +alternative_if ARM64_HAS_CACHE_IDC > + dsb ishst > + b .Ldc_skip_\@ > +alternative_else_nop_endif > + dcache_line_size x2, x3 > + sub x3, x2, #1 > + bic x4, x0, x3 > +.Ldc_loop_\@: > +user_alt "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE, \fixup > + add x4, x4, x2 > + cmp x4, x1 > + b.lo .Ldc_loop_\@ > + dsb ish As on the prior patch, I reckon it'd be nicer overall to align with the *by_line macros and have an explicit _cond_extable here, e.g. | .Ldc_op\@: | alternative_insn "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE | add x4, x4, x2 | cmp x4, x1 | b.lo .Ldc_op\@ | dsb ish | ... | // just before the .endm | _cond_extable .Ldc_op\@, \fixup ... and with some rework it might be possible to use dcache_by_line_op directly here (it currently clobbers the base and end, so can't be used as-is). Thanks, Mark. > + > +.Ldc_skip_\@: > +alternative_if ARM64_HAS_CACHE_DIC > + isb > + b .Lic_skip_\@ > +alternative_else_nop_endif > + invalidate_icache_by_line x0, x1, x2, x3, \fixup > +.Lic_skip_\@: > +.endm > + > /* > * flush_icache_range(start,end) > * > @@ -25,7 +60,9 @@ > * - end - virtual end address of region > */ > SYM_FUNC_START(__flush_icache_range) > - /* FALLTHROUGH */ > + __flush_cache_range > + ret > +SYM_FUNC_END(__flush_icache_range) > > /* > * __flush_cache_user_range(start,end) > @@ -39,34 +76,15 @@ SYM_FUNC_START(__flush_icache_range) > */ > SYM_FUNC_START(__flush_cache_user_range) > uaccess_ttbr0_enable x2, x3, x4 > -alternative_if ARM64_HAS_CACHE_IDC > - dsb ishst > - b 7f > -alternative_else_nop_endif > - dcache_line_size x2, x3 > - sub x3, x2, #1 > - bic x4, x0, x3 > -1: > -user_alt "dc cvau, x4", "dc civac, x4", ARM64_WORKAROUND_CLEAN_CACHE, 9f > - add x4, x4, x2 > - cmp x4, x1 > - b.lo 1b > - dsb ish > > -7: > -alternative_if ARM64_HAS_CACHE_DIC > - isb > - b 8f > -alternative_else_nop_endif > - invalidate_icache_by_line x0, x1, x2, x3, 9f > -8: mov x0, #0 > + __flush_cache_range 2f > + mov x0, xzr > 1: > uaccess_ttbr0_disable x1, x2 > ret > -9: > +2: > mov x0, #-EFAULT > b 1b > -SYM_FUNC_END(__flush_icache_range) > SYM_FUNC_END(__flush_cache_user_range) > > /* > -- > 2.31.1.751.gd2f1c929bd-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel