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From: Mark Rutland <mark.rutland@arm.com>
To: Fuad Tabba <tabba@google.com>
Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org,
	catalin.marinas@arm.com, maz@kernel.org, ardb@kernel.org,
	james.morse@arm.com, alexandru.elisei@arm.com,
	suzuki.poulose@arm.com, robin.murphy@arm.com
Subject: Re: [PATCH v3 16/18] arm64: sync_icache_aliases to take end parameter instead of size
Date: Thu, 20 May 2021 17:34:18 +0100	[thread overview]
Message-ID: <20210520163418.GU17233@C02TD0UTHF1T.local> (raw)
In-Reply-To: <20210520124406.2731873-17-tabba@google.com>

On Thu, May 20, 2021 at 01:44:04PM +0100, Fuad Tabba wrote:
> To be consistent with other functions with similar names and
> functionality in cacheflush.h, cache.S, and cachetlb.rst, change
> to specify the range in terms of start and end, as opposed to
> start and size.
> 
> No functional change intended.
> 
> Reported-by: Will Deacon <will@kernel.org>
> Signed-off-by: Fuad Tabba <tabba@google.com>
> ---
>  arch/arm64/include/asm/cacheflush.h |  2 +-
>  arch/arm64/kernel/probes/uprobes.c  |  2 +-
>  arch/arm64/mm/flush.c               | 21 +++++++++++----------
>  3 files changed, 13 insertions(+), 12 deletions(-)
> 
> diff --git a/arch/arm64/include/asm/cacheflush.h b/arch/arm64/include/asm/cacheflush.h
> index f86723047315..70b389a8dea5 100644
> --- a/arch/arm64/include/asm/cacheflush.h
> +++ b/arch/arm64/include/asm/cacheflush.h
> @@ -64,7 +64,7 @@ extern void __clean_dcache_area_poc(unsigned long start, unsigned long end);
>  extern void __clean_dcache_area_pop(unsigned long start, unsigned long end);
>  extern void __clean_dcache_area_pou(unsigned long start, unsigned long end);
>  extern long __flush_cache_user_range(unsigned long start, unsigned long end);
> -extern void sync_icache_aliases(void *kaddr, unsigned long len);
> +extern void sync_icache_aliases(unsigned long start, unsigned long end);
>  
>  static inline void flush_icache_range(unsigned long start, unsigned long end)
>  {
> diff --git a/arch/arm64/kernel/probes/uprobes.c b/arch/arm64/kernel/probes/uprobes.c
> index 2c247634552b..9be668f3f034 100644
> --- a/arch/arm64/kernel/probes/uprobes.c
> +++ b/arch/arm64/kernel/probes/uprobes.c
> @@ -21,7 +21,7 @@ void arch_uprobe_copy_ixol(struct page *page, unsigned long vaddr,
>  	memcpy(dst, src, len);
>  
>  	/* flush caches (dcache/icache) */
> -	sync_icache_aliases(dst, len);
> +	sync_icache_aliases((unsigned long)dst, (unsigned long)dst + len);
>  
>  	kunmap_atomic(xol_page_kaddr);
>  }
> diff --git a/arch/arm64/mm/flush.c b/arch/arm64/mm/flush.c
> index a69d745fb1dc..143f625e7727 100644
> --- a/arch/arm64/mm/flush.c
> +++ b/arch/arm64/mm/flush.c
> @@ -14,28 +14,26 @@
>  #include <asm/cache.h>
>  #include <asm/tlbflush.h>
>  
> -void sync_icache_aliases(void *kaddr, unsigned long len)
> +void sync_icache_aliases(unsigned long start, unsigned long end)
>  {
> -	unsigned long addr = (unsigned long)kaddr;
> -
>  	if (icache_is_aliasing()) {
> -		__clean_dcache_area_pou(kaddr, kaddr + len);
> +		__clean_dcache_area_pou(start, end);
>  		__flush_icache_all();
>  	} else {
>  		/*
>  		 * Don't issue kick_all_cpus_sync() after I-cache invalidation
>  		 * for user mappings.
>  		 */
> -		__flush_icache_range(addr, addr + len);
> +		__flush_icache_range(start, end);
>  	}
>  }
>  
>  static void flush_ptrace_access(struct vm_area_struct *vma, struct page *page,
> -				unsigned long uaddr, void *kaddr,
> -				unsigned long len)
> +				unsigned long uaddr, unsigned long start,
> +				unsigned long end)

Can we please drop the `uaddr` argument here?

Generally, for functions which take both a `uaddr` and a `kaddr`, it's
best to pass a length argument, since that can be applied to either
base. Since we don't use the `uaddr` here it's simpler to remove that.

With that gone:

Acked-by: Mark Rutland <mark.rutland@arm.com>

Mark.

>  {
>  	if (vma->vm_flags & VM_EXEC)
> -		sync_icache_aliases(kaddr, len);
> +		sync_icache_aliases(start, end);
>  }
>  
>  /*
> @@ -48,7 +46,8 @@ void copy_to_user_page(struct vm_area_struct *vma, struct page *page,
>  		       unsigned long len)
>  {
>  	memcpy(dst, src, len);
> -	flush_ptrace_access(vma, page, uaddr, dst, len);
> +	flush_ptrace_access(vma, page, uaddr, (unsigned long)dst,
> +			    (unsigned long)dst + len);
>  }
>  
>  void __sync_icache_dcache(pte_t pte)
> @@ -56,7 +55,9 @@ void __sync_icache_dcache(pte_t pte)
>  	struct page *page = pte_page(pte);
>  
>  	if (!test_and_set_bit(PG_dcache_clean, &page->flags))
> -		sync_icache_aliases(page_address(page), page_size(page));
> +		sync_icache_aliases((unsigned long)page_address(page),
> +				    (unsigned long)page_address(page) +
> +					    page_size(page));
>  }
>  EXPORT_SYMBOL_GPL(__sync_icache_dcache);
>  
> -- 
> 2.31.1.751.gd2f1c929bd-goog
> 

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  reply	other threads:[~2021-05-20 16:36 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-20 12:43 [PATCH v3 00/18] Tidy up cache.S Fuad Tabba
2021-05-20 12:43 ` [PATCH v3 01/18] arm64: assembler: replace `kaddr` with `addr` Fuad Tabba
2021-05-20 12:43 ` [PATCH v3 02/18] arm64: assembler: add conditional cache fixups Fuad Tabba
2021-05-20 12:43 ` [PATCH v3 03/18] arm64: Apply errata to swsusp_arch_suspend_exit Fuad Tabba
2021-05-20 12:46   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 04/18] arm64: assembler: user_alt label optional Fuad Tabba
2021-05-20 12:57   ` Mark Rutland
2021-05-21 11:46     ` Fuad Tabba
2021-05-21 13:05       ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 05/18] arm64: Do not enable uaccess for flush_icache_range Fuad Tabba
2021-05-20 14:02   ` Mark Rutland
2021-05-20 15:37     ` Mark Rutland
2021-05-21 12:18       ` Mark Rutland
2021-05-25 11:18   ` Catalin Marinas
2021-05-20 12:43 ` [PATCH v3 06/18] arm64: Do not enable uaccess for invalidate_icache_range Fuad Tabba
2021-05-20 14:13   ` Mark Rutland
2021-05-25 11:18   ` Catalin Marinas
2021-05-20 12:43 ` [PATCH v3 07/18] arm64: Downgrade flush_icache_range to invalidate Fuad Tabba
2021-05-20 14:15   ` Mark Rutland
2021-05-25 11:18   ` Catalin Marinas
2021-05-20 12:43 ` [PATCH v3 08/18] arm64: Move documentation of dcache_by_line_op Fuad Tabba
2021-05-20 14:17   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 09/18] arm64: Fix comments to refer to correct function __flush_icache_range Fuad Tabba
2021-05-20 14:18   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 10/18] arm64: __inval_dcache_area to take end parameter instead of size Fuad Tabba
2021-05-20 15:46   ` Mark Rutland
2021-05-20 12:43 ` [PATCH v3 11/18] arm64: dcache_by_line_op " Fuad Tabba
2021-05-20 15:48   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 12/18] arm64: __flush_dcache_area " Fuad Tabba
2021-05-20 16:06   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 13/18] arm64: __clean_dcache_area_poc " Fuad Tabba
2021-05-20 16:16   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 14/18] arm64: __clean_dcache_area_pop " Fuad Tabba
2021-05-20 16:19   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 15/18] arm64: __clean_dcache_area_pou " Fuad Tabba
2021-05-20 16:24   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 16/18] arm64: sync_icache_aliases " Fuad Tabba
2021-05-20 16:34   ` Mark Rutland [this message]
2021-05-20 12:44 ` [PATCH v3 17/18] arm64: Fix cache maintenance function comments Fuad Tabba
2021-05-20 16:48   ` Mark Rutland
2021-05-20 12:44 ` [PATCH v3 18/18] arm64: Rename arm64-internal cache maintenance functions Fuad Tabba
2021-05-20 17:01   ` Mark Rutland

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