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[83.57.168.235]) by smtp.gmail.com with ESMTPSA id z19sm491653edr.77.2021.06.03.02.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Jun 2021 02:03:12 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 0/6] target/microblaze: Clean up MMU translation failed path Date: Thu, 3 Jun 2021 11:03:04 +0200 Message-Id: <20210603090310.2749892-1-f4bug@amsat.org> X-Mailer: git-send-email 2.26.3 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass client-ip=2a00:1450:4864:20::636; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-ej1-x636.google.com X-Spam_score_int: -14 X-Spam_score: -1.5 X-Spam_bar: - X-Spam_report: (-1.5 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.248, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Edgar E. Iglesias" , Richard Henderson , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" Hi Edgar,=0D =0D While reviewing/auditing how each arch handles failed MMU=0D transactions, I noticed some confusing code regarding the=0D On-chip Peripheral Bus (OPB) interface which is currently=0D not implemented. I took some notes and re-ordered the code=0D a bit, resulting in this series.=0D =0D Q: Should we exit gracefully in mb_cpu_realizefn() if the=0D user requests features that are not implemented?=0D =0D Thanks,=0D =0D Phil.=0D =0D Philippe Mathieu-Daud=C3=A9 (6):=0D target/microblaze: Use the IEC binary prefix definitions=0D target/microblaze: Extract FPU helpers to fpu_helper.c=0D target/microblaze: Assert transaction failures have exception enabled=0D target/microblaze: Fix Exception Status Register 'Cause' definitions=0D target/microblaze: Replace magic values by proper definitions=0D target/microblaze: Set OPB bits in tlb_fill, not in transaction_failed=0D =0D target/microblaze/cpu.h | 8 +-=0D target/microblaze/fpu_helper.c | 308 +++++++++++++++++++++++++++++++++=0D target/microblaze/helper.c | 35 +++-=0D target/microblaze/mmu.c | 5 +-=0D target/microblaze/op_helper.c | 304 +-------------------------------=0D target/microblaze/meson.build | 1 +=0D 6 files changed, 349 insertions(+), 312 deletions(-)=0D create mode 100644 target/microblaze/fpu_helper.c=0D =0D -- =0D 2.26.3=0D =0D