From: Hao Wu <wuhaotsh@google.com>
To: peter.maydell@linaro.org
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, minyard@acm.org,
wuhaotsh@google.com, titusr@google.com, venture@google.com,
Avi.Fishman@nuvoton.com, kfting@nuvoton.com,
hskinnemoen@google.com
Subject: [PATCH 3/7] hw/adc: Fix CONV bit in NPCM7XX ADC CON register
Date: Fri, 13 Aug 2021 16:33:49 -0700 [thread overview]
Message-ID: <20210813233353.2099459-4-wuhaotsh@google.com> (raw)
In-Reply-To: <20210813233353.2099459-1-wuhaotsh@google.com>
The correct bit for the CONV bit in NPCM7XX ADC is bit 13. This patch
fixes that in the module, and also lower the IRQ when the guest
is done handling an interrupt event from the ADC module.
Signed-off-by: Hao Wu <wuhaotsh@google.com>
Reviewed-by: Patrick Venture<venture@google.com>
---
hw/adc/npcm7xx_adc.c | 2 +-
tests/qtest/npcm7xx_adc-test.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c
index 0f0a9f63e2..47fb9e5f74 100644
--- a/hw/adc/npcm7xx_adc.c
+++ b/hw/adc/npcm7xx_adc.c
@@ -36,7 +36,7 @@ REG32(NPCM7XX_ADC_DATA, 0x4)
#define NPCM7XX_ADC_CON_INT BIT(18)
#define NPCM7XX_ADC_CON_EN BIT(17)
#define NPCM7XX_ADC_CON_RST BIT(16)
-#define NPCM7XX_ADC_CON_CONV BIT(14)
+#define NPCM7XX_ADC_CON_CONV BIT(13)
#define NPCM7XX_ADC_CON_DIV(rv) extract32(rv, 1, 8)
#define NPCM7XX_ADC_MAX_RESULT 1023
diff --git a/tests/qtest/npcm7xx_adc-test.c b/tests/qtest/npcm7xx_adc-test.c
index 5ce8ce13b3..aaf127dd42 100644
--- a/tests/qtest/npcm7xx_adc-test.c
+++ b/tests/qtest/npcm7xx_adc-test.c
@@ -50,7 +50,7 @@
#define CON_INT BIT(18)
#define CON_EN BIT(17)
#define CON_RST BIT(16)
-#define CON_CONV BIT(14)
+#define CON_CONV BIT(13)
#define CON_DIV(rv) extract32(rv, 1, 8)
#define FST_RDST BIT(1)
--
2.33.0.rc1.237.g0d66db33f3-goog
next prev parent reply other threads:[~2021-08-13 23:40 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-13 23:33 [PATCH 0/7] Misc NPCM7XX patches Hao Wu
2021-08-13 23:33 ` [PATCH 1/7] hw/i2c: Clear ACK bit in NPCM7xx SMBus module Hao Wu
2021-08-13 23:33 ` [PATCH 2/7] hw/i2c: Read FIFO during RXF_CTL change in NPCM7XX SMBus Hao Wu
2021-08-13 23:33 ` Hao Wu [this message]
2021-08-13 23:33 ` [PATCH 4/7] hw/adc: Make adci[*] R/W in NPCM7XX ADC Hao Wu
2021-08-20 7:28 ` Philippe Mathieu-Daudé
2021-08-13 23:33 ` [PATCH 5/7] hw/nvram: Add a new auxiliary function to init at24c eeprom Hao Wu
2021-08-19 13:59 ` Peter Maydell
2021-08-13 23:33 ` [PATCH 6/7] hw/arm: quanta-gbs-bmc add i2c devices Hao Wu
2021-08-19 13:55 ` Peter Maydell
2021-08-13 23:33 ` [PATCH 7/7] hw/arm: Use unit number in quanta-gsj eeprom files Hao Wu
2021-08-19 14:00 ` [PATCH 0/7] Misc NPCM7XX patches Peter Maydell
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