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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: "Aurelien Jarno" <aurelien@aurel32.net>,
	"Aleksandar Rikalo" <aleksandar.rikalo@syrmia.com>,
	"Richard Henderson" <richard.henderson@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>
Subject: [PULL 04/28] target/mips: Merge 32-bit/64-bit Release6 decodetree definitions
Date: Wed, 25 Aug 2021 15:01:47 +0200	[thread overview]
Message-ID: <20210825130211.1542338-5-f4bug@amsat.org> (raw)
In-Reply-To: <20210825130211.1542338-1-f4bug@amsat.org>

We don't need to maintain 2 sets of decodetree definitions.
Merge them into a single file.

Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20210801234202.3167676-4-f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/mips/tcg/mips64r6.decode               | 27 -------------------
 .../mips/tcg/{mips32r6.decode => rel6.decode} | 13 +++++++++
 target/mips/tcg/rel6_translate.c              | 16 ++++-------
 target/mips/tcg/meson.build                   |  3 +--
 4 files changed, 19 insertions(+), 40 deletions(-)
 delete mode 100644 target/mips/tcg/mips64r6.decode
 rename target/mips/tcg/{mips32r6.decode => rel6.decode} (69%)

diff --git a/target/mips/tcg/mips64r6.decode b/target/mips/tcg/mips64r6.decode
deleted file mode 100644
index b58d8009ccd..00000000000
--- a/target/mips/tcg/mips64r6.decode
+++ /dev/null
@@ -1,27 +0,0 @@
-# MIPS64 Release 6 instruction set
-#
-# Copyright (C) 2020  Philippe Mathieu-Daudé
-#
-# SPDX-License-Identifier: LGPL-2.1-or-later
-#
-# Reference:
-#       MIPS Architecture for Programmers Volume II-A
-#       The MIPS64 Instruction Set Reference Manual, Revision 6.06
-#       (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
-#
-
-&rtype              rs rt rd sa !extern
-
-&REMOVED            !extern
-
-@lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &rtype
-
-DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
-
-REMOVED             011010 ----- ----- ----------------     # LDL
-REMOVED             011011 ----- ----- ----------------     # LDR
-REMOVED             101100 ----- ----- ----------------     # SDL
-REMOVED             101101 ----- ----- ----------------     # SDR
-
-REMOVED             110100 ----- ----- ----------------     # LLD
-REMOVED             111100 ----- ----- ----------------     # SCD
diff --git a/target/mips/tcg/mips32r6.decode b/target/mips/tcg/rel6.decode
similarity index 69%
rename from target/mips/tcg/mips32r6.decode
rename to target/mips/tcg/rel6.decode
index 837c991edc5..ed069c51662 100644
--- a/target/mips/tcg/mips32r6.decode
+++ b/target/mips/tcg/rel6.decode
@@ -5,21 +5,29 @@
 # SPDX-License-Identifier: LGPL-2.1-or-later
 #
 # Reference:
+#
 #       MIPS Architecture for Programmers Volume II-A
 #       The MIPS32 Instruction Set Reference Manual, Revision 6.06
 #       (Document Number: MD00086-2B-MIPS32BIS-AFP-06.06)
 #
+#       MIPS Architecture for Programmers Volume II-A
+#       The MIPS64 Instruction Set Reference Manual, Revision 6.06
+#       (Document Number: MD00087-2B-MIPS64BIS-AFP-6.06)
 
 &rtype              rs rt rd sa
 
 @lsa                ...... rs:5 rt:5 rd:5 ... sa:2 ......   &rtype
 
 LSA                 000000 ..... ..... ..... 000 .. 000101  @lsa
+DLSA                000000 ..... ..... ..... 000 .. 010101  @lsa
 
 REMOVED             010011 ----- ----- ----- ----- ------   # COP1X (COP3)
 
 REMOVED             011100 ----- ----- ----- ----- ------   # SPECIAL2
 
+REMOVED             011010 ----- ----- ----------------     # LDL
+REMOVED             011011 ----- ----- ----------------     # LDR
+
 REMOVED             011111 ----- ----- ----------  011001   # LWLE
 REMOVED             011111 ----- ----- ----------  011010   # LWRE
 REMOVED             011111 ----- ----- ----------  100001   # SWLE
@@ -28,9 +36,14 @@ REMOVED             011111 ----- ----- ----------  100010   # SWRE
 REMOVED             100010 ----- ----- ----------------     # LWL
 REMOVED             100110 ----- ----- ----------------     # LWR
 REMOVED             101010 ----- ----- ----------------     # SWL
+REMOVED             101100 ----- ----- ----------------     # SDL
+REMOVED             101101 ----- ----- ----------------     # SDR
 REMOVED             101110 ----- ----- ----------------     # SWR
 
 REMOVED             101111 ----- ----- ----------------     # CACHE
+
 REMOVED             110000 ----- ----- ----------------     # LL
 REMOVED             110011 ----- ----- ----------------     # PREF
+REMOVED             110100 ----- ----- ----------------     # LLD
 REMOVED             111000 ----- ----- ----------------     # SC
+REMOVED             111100 ----- ----- ----------------     # SCD
diff --git a/target/mips/tcg/rel6_translate.c b/target/mips/tcg/rel6_translate.c
index 0354370927d..ae2e023a817 100644
--- a/target/mips/tcg/rel6_translate.c
+++ b/target/mips/tcg/rel6_translate.c
@@ -13,9 +13,8 @@
 #include "exec/helper-gen.h"
 #include "translate.h"
 
-/* Include the auto-generated decoder.  */
-#include "decode-mips32r6.c.inc"
-#include "decode-mips64r6.c.inc"
+/* Include the auto-generated decoders.  */
+#include "decode-rel6.c.inc"
 
 bool trans_REMOVED(DisasContext *ctx, arg_REMOVED *a)
 {
@@ -31,13 +30,8 @@ static bool trans_LSA(DisasContext *ctx, arg_rtype *a)
 
 static bool trans_DLSA(DisasContext *ctx, arg_rtype *a)
 {
+    if (TARGET_LONG_BITS != 64) {
+        return false;
+    }
     return gen_dlsa(ctx, a->rd, a->rt, a->rs, a->sa);
 }
-
-bool decode_isa_rel6(DisasContext *ctx, uint32_t insn)
-{
-    if (TARGET_LONG_BITS == 64 && decode_mips64r6(ctx, insn)) {
-        return true;
-    }
-    return decode_mips32r6(ctx, insn);
-}
diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build
index bf4001e5741..70fa3dd57df 100644
--- a/target/mips/tcg/meson.build
+++ b/target/mips/tcg/meson.build
@@ -1,6 +1,5 @@
 gen = [
-  decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'),
-  decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'),
+  decodetree.process('rel6.decode', extra_args: ['--decode=decode_isa_rel6']),
   decodetree.process('msa.decode', extra_args: '--decode=decode_ase_msa'),
   decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'),
 ]
-- 
2.31.1



  parent reply	other threads:[~2021-08-25 13:06 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-25 13:01 [PULL 00/28] MIPS patches for 2021-08-25 Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 01/28] target/mips: Remove JR opcode unused arguments Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 02/28] target/mips: Simplify PREF opcode Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 03/28] target/mips: Decode vendor extensions before MIPS ISAs Philippe Mathieu-Daudé
2021-08-25 13:01 ` Philippe Mathieu-Daudé [this message]
2021-08-25 13:01 ` [PULL 05/28] target/mips: Rename 'rtype' as 'r' Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 06/28] target/mips: Introduce generic TRANS() macro for decodetree helpers Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 07/28] target/mips: Extract NEC Vr54xx helper definitions Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 08/28] target/mips: Extract NEC Vr54xx helpers to vr54xx_helper.c Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 09/28] target/mips: Introduce decodetree structure for NEC Vr54xx extension Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 10/28] target/mips: Convert Vr54xx MACC* opcodes to decodetree Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 11/28] target/mips: Convert Vr54xx MUL* " Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 12/28] target/mips: Convert Vr54xx MSA* " Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 13/28] target/mips: Document Loongson-3A CPU definitions Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 14/28] target/mips: Allow Loongson 3A1000 to use up to 48-bit VAddr Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 15/28] target/mips: Remove duplicated check_cp1_enabled() calls in Loongson EXT Philippe Mathieu-Daudé
2021-08-25 13:01 ` [PULL 16/28] target/mips: Remove gen_helper_0e3i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 17/28] target/mips: Remove gen_helper_1e2i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 18/28] target/mips: Use tcg_constant_i32() in gen_helper_0e2i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 19/28] target/mips: Simplify gen_helper() macros by using tcg_constant_i32() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 20/28] target/mips: Inline gen_helper_1e1i() call in op_ld_INSN() macros Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 21/28] target/mips: Inline gen_helper_0e0i() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 22/28] target/mips: Use tcg_constant_i32() in generate_exception_err() Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 23/28] target/mips: Define gen_helper() macros in translate.h Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 24/28] target/mips: Call cpu_is_bigendian & inline GET_OFFSET in ld/st helpers Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 25/28] target/mips: Replace GET_LMASK() macro by get_lmask(32) function Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 26/28] target/mips: Replace GET_LMASK64() macro by get_lmask(64) function Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 27/28] target/mips: Store CP0_Config0 in DisasContext Philippe Mathieu-Daudé
2021-08-25 13:02 ` [PULL 28/28] target/mips: Replace TARGET_WORDS_BIGENDIAN by cpu_is_bigendian() Philippe Mathieu-Daudé
2021-08-26  9:41 ` [PULL 00/28] MIPS patches for 2021-08-25 Peter Maydell

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