From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 17/51] target/arm: Implement MVE fp scalar comparisons
Date: Wed, 1 Sep 2021 11:36:19 +0100 [thread overview]
Message-ID: <20210901103653.13435-18-peter.maydell@linaro.org> (raw)
In-Reply-To: <20210901103653.13435-1-peter.maydell@linaro.org>
Implement the MVE fp scalar comparisons VCMP and VPT.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/helper-mve.h | 18 +++++++++++
target/arm/mve.decode | 61 +++++++++++++++++++++++++++++--------
target/arm/mve_helper.c | 62 ++++++++++++++++++++++++++++++--------
target/arm/translate-mve.c | 14 +++++++++
4 files changed, 131 insertions(+), 24 deletions(-)
diff --git a/target/arm/helper-mve.h b/target/arm/helper-mve.h
index 0c15c531641..9ee841cdf01 100644
--- a/target/arm/helper-mve.h
+++ b/target/arm/helper-mve.h
@@ -831,6 +831,24 @@ DEF_HELPER_FLAGS_3(mve_vfcmpgts, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vfcmpleh, TCG_CALL_NO_WG, void, env, ptr, ptr)
DEF_HELPER_FLAGS_3(mve_vfcmples, TCG_CALL_NO_WG, void, env, ptr, ptr)
+DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vfcmpeq_scalars, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vfcmpne_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vfcmpne_scalars, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vfcmpge_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vfcmpge_scalars, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vfcmplt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vfcmplt_scalars, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vfcmpgt_scalars, TCG_CALL_NO_WG, void, env, ptr, i32)
+
+DEF_HELPER_FLAGS_3(mve_vfcmple_scalarh, TCG_CALL_NO_WG, void, env, ptr, i32)
+DEF_HELPER_FLAGS_3(mve_vfcmple_scalars, TCG_CALL_NO_WG, void, env, ptr, i32)
+
DEF_HELPER_FLAGS_4(mve_vfadd_scalarh, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(mve_vfadd_scalars, TCG_CALL_NO_WG, void, env, ptr, ptr, i32)
diff --git a/target/arm/mve.decode b/target/arm/mve.decode
index 49b7ef35937..f1b8afb4778 100644
--- a/target/arm/mve.decode
+++ b/target/arm/mve.decode
@@ -127,6 +127,11 @@
@vcmp_fp .... .... .... qn:3 . .... .... .... .... &vcmp \
qm=%qm size=%2op_fp_scalar_size mask=%mask_22_13
+# Bit 28 is a 2op_fp_scalar_size bit, but we do not decode it in this
+# format to avoid complicated overlapping-instruction-groups
+@vcmp_fp_scalar .... .... .... qn:3 . .... .... .... rm:4 &vcmp_scalar \
+ mask=%mask_22_13
+
@vmaxv .... .... .... size:2 .. rda:4 .... .... .... &vmaxv qm=%qm
@2op_fp .... .... .... .... .... .... .... .... &2op \
@@ -400,8 +405,10 @@ VDUP 1110 1110 1 0 10 ... 0 .... 1011 . 0 0 1 0000 @vdup size=2
VIWDUP 1110 1110 0 . .. ... 1 ... 0 1111 . 110 ... . @viwdup
}
{
- VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup
- VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup
+ VCMPGT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_scalar size=2
+ VCMPLE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_scalar size=2
+ VDDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 111 . @vidup
+ VDWDUP 1110 1110 0 . .. ... 1 ... 1 1111 . 110 ... . @viwdup
}
# multiply-add long dual accumulate
@@ -480,8 +487,17 @@ VMLADAV_U 1111 1110 1111 ... 0 ... . 1111 . 0 . 0 ... 1 @vmladav_nosz
# Scalar operations
-VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar
-VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar
+{
+ VCMPEQ_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_scalar size=2
+ VCMPNE_fp_scalar 1110 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_scalar size=2
+ VADD_scalar 1110 1110 0 . .. ... 1 ... 0 1111 . 100 .... @2scalar
+}
+
+{
+ VCMPLT_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_scalar size=2
+ VCMPGE_fp_scalar 1110 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_scalar size=2
+ VSUB_scalar 1110 1110 0 . .. ... 1 ... 1 1111 . 100 .... @2scalar
+}
{
VSHL_S_scalar 1110 1110 0 . 11 .. 01 ... 1 1110 0110 .... @shl_scalar
@@ -711,17 +727,38 @@ VSHLC 111 0 1110 1 . 1 imm:5 ... 0 1111 1100 rdm:4 qd=%qd
}
{
- VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101
- VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
- VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 0 0 .... @vcmp_scalar
+ VPNOT 1111 1110 0 0 11 000 1 000 0 1111 0100 1101
+ VPST 1111 1110 0 . 11 000 1 ... 0 1111 0100 1101 mask=%mask_22_13
+ VCMPEQ_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 0100 .... @vcmp_fp_scalar size=1
+ VCMPEQ_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0100 .... @vcmp_scalar
}
-VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 0 0 .... @vcmp_scalar
+
+{
+ VCMPNE_fp_scalar 1111 1110 0 . 11 ... 1 ... 0 1111 1100 .... @vcmp_fp_scalar size=1
+ VCMPNE_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1100 .... @vcmp_scalar
+}
+
+{
+ VCMPGT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0110 .... @vcmp_fp_scalar size=1
+ VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0110 .... @vcmp_scalar
+}
+
+{
+ VCMPLE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1110 .... @vcmp_fp_scalar size=1
+ VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1110 .... @vcmp_scalar
+}
+
+{
+ VCMPGE_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 0100 .... @vcmp_fp_scalar size=1
+ VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0100 .... @vcmp_scalar
+}
+{
+ VCMPLT_fp_scalar 1111 1110 0 . 11 ... 1 ... 1 1111 1100 .... @vcmp_fp_scalar size=1
+ VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1100 .... @vcmp_scalar
+}
+
VCMPCS_scalar 1111 1110 0 . .. ... 1 ... 0 1111 0 1 1 0 .... @vcmp_scalar
VCMPHI_scalar 1111 1110 0 . .. ... 1 ... 0 1111 1 1 1 0 .... @vcmp_scalar
-VCMPGE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 0 0 .... @vcmp_scalar
-VCMPLT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 0 0 .... @vcmp_scalar
-VCMPGT_scalar 1111 1110 0 . .. ... 1 ... 1 1111 0 1 1 0 .... @vcmp_scalar
-VCMPLE_scalar 1111 1110 0 . .. ... 1 ... 1 1111 1 1 1 0 .... @vcmp_scalar
# 2-operand FP
VADD_fp 1110 1111 0 . 0 . ... 0 ... 0 1101 . 1 . 0 ... 0 @2op_fp
diff --git a/target/arm/mve_helper.c b/target/arm/mve_helper.c
index 07a1ab88814..891926c124d 100644
--- a/target/arm/mve_helper.c
+++ b/target/arm/mve_helper.c
@@ -3191,6 +3191,44 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum)
mve_advance_vpt(env); \
}
+#define DO_VCMP_FP_SCALAR(OP, ESIZE, TYPE, FN) \
+ void HELPER(glue(mve_, OP))(CPUARMState *env, void *vn, \
+ uint32_t rm) \
+ { \
+ TYPE *n = vn; \
+ uint16_t mask = mve_element_mask(env); \
+ uint16_t eci_mask = mve_eci_mask(env); \
+ uint16_t beatpred = 0; \
+ uint16_t emask = MAKE_64BIT_MASK(0, ESIZE); \
+ unsigned e; \
+ float_status *fpst; \
+ float_status scratch_fpst; \
+ bool r; \
+ for (e = 0; e < 16 / ESIZE; e++, emask <<= ESIZE) { \
+ if ((mask & emask) == 0) { \
+ continue; \
+ } \
+ fpst = (ESIZE == 2) ? &env->vfp.standard_fp_status_f16 : \
+ &env->vfp.standard_fp_status; \
+ if (!(mask & (1 << (e * ESIZE)))) { \
+ /* We need the result but without updating flags */ \
+ scratch_fpst = *fpst; \
+ fpst = &scratch_fpst; \
+ } \
+ r = FN(n[H##ESIZE(e)], (TYPE)rm, fpst); \
+ /* Comparison sets 0/1 bits for each byte in the element */ \
+ beatpred |= r * emask; \
+ } \
+ beatpred &= mask; \
+ env->v7m.vpr = (env->v7m.vpr & ~(uint32_t)eci_mask) | \
+ (beatpred & eci_mask); \
+ mve_advance_vpt(env); \
+ }
+
+#define DO_VCMP_FP_BOTH(VOP, SOP, ESIZE, TYPE, FN) \
+ DO_VCMP_FP(VOP, ESIZE, TYPE, FN) \
+ DO_VCMP_FP_SCALAR(SOP, ESIZE, TYPE, FN)
+
/*
* Some care is needed here to get the correct result for the unordered case.
* Architecturally EQ, GE and GT are defined to be false for unordered, but
@@ -3203,20 +3241,20 @@ DO_FP_VMAXMINV(vminnmavs, 4, float32, true, float32_minnum)
#define DO_GT16(X, Y, S) float16_lt(Y, X, S)
#define DO_GT32(X, Y, S) float32_lt(Y, X, S)
-DO_VCMP_FP(vfcmpeqh, 2, float16, float16_eq)
-DO_VCMP_FP(vfcmpeqs, 4, float32, float32_eq)
+DO_VCMP_FP_BOTH(vfcmpeqh, vfcmpeq_scalarh, 2, float16, float16_eq)
+DO_VCMP_FP_BOTH(vfcmpeqs, vfcmpeq_scalars, 4, float32, float32_eq)
-DO_VCMP_FP(vfcmpneh, 2, float16, !float16_eq)
-DO_VCMP_FP(vfcmpnes, 4, float32, !float32_eq)
+DO_VCMP_FP_BOTH(vfcmpneh, vfcmpne_scalarh, 2, float16, !float16_eq)
+DO_VCMP_FP_BOTH(vfcmpnes, vfcmpne_scalars, 4, float32, !float32_eq)
-DO_VCMP_FP(vfcmpgeh, 2, float16, DO_GE16)
-DO_VCMP_FP(vfcmpges, 4, float32, DO_GE32)
+DO_VCMP_FP_BOTH(vfcmpgeh, vfcmpge_scalarh, 2, float16, DO_GE16)
+DO_VCMP_FP_BOTH(vfcmpges, vfcmpge_scalars, 4, float32, DO_GE32)
-DO_VCMP_FP(vfcmplth, 2, float16, !DO_GE16)
-DO_VCMP_FP(vfcmplts, 4, float32, !DO_GE32)
+DO_VCMP_FP_BOTH(vfcmplth, vfcmplt_scalarh, 2, float16, !DO_GE16)
+DO_VCMP_FP_BOTH(vfcmplts, vfcmplt_scalars, 4, float32, !DO_GE32)
-DO_VCMP_FP(vfcmpgth, 2, float16, DO_GT16)
-DO_VCMP_FP(vfcmpgts, 4, float32, DO_GT32)
+DO_VCMP_FP_BOTH(vfcmpgth, vfcmpgt_scalarh, 2, float16, DO_GT16)
+DO_VCMP_FP_BOTH(vfcmpgts, vfcmpgt_scalars, 4, float32, DO_GT32)
-DO_VCMP_FP(vfcmpleh, 2, float16, !DO_GT16)
-DO_VCMP_FP(vfcmples, 4, float32, !DO_GT32)
+DO_VCMP_FP_BOTH(vfcmpleh, vfcmple_scalarh, 2, float16, !DO_GT16)
+DO_VCMP_FP_BOTH(vfcmples, vfcmple_scalars, 4, float32, !DO_GT32)
diff --git a/target/arm/translate-mve.c b/target/arm/translate-mve.c
index da14a6f790e..e8a3dec6683 100644
--- a/target/arm/translate-mve.c
+++ b/target/arm/translate-mve.c
@@ -1771,6 +1771,20 @@ DO_VCMP(VCMPLE, vcmple)
return false; \
} \
return do_vcmp(s, a, fns[a->size]); \
+ } \
+ static bool trans_##INSN##_scalar(DisasContext *s, \
+ arg_vcmp_scalar *a) \
+ { \
+ static MVEGenScalarCmpFn * const fns[] = { \
+ NULL, \
+ gen_helper_mve_##FN##_scalarh, \
+ gen_helper_mve_##FN##_scalars, \
+ NULL, \
+ }; \
+ if (!dc_isar_feature(aa32_mve_fp, s)) { \
+ return false; \
+ } \
+ return do_vcmp_scalar(s, a, fns[a->size]); \
}
DO_VCMP_FP(VCMPEQ_fp, vfcmpeq)
--
2.20.1
next prev parent reply other threads:[~2021-09-01 10:41 UTC|newest]
Thread overview: 53+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-01 10:36 [PULL 00/51] target-arm queue Peter Maydell
2021-09-01 10:36 ` [PULL 01/51] tests: Remove uses of deprecated raspi2/raspi3 machine names Peter Maydell
2021-09-01 10:36 ` [PULL 02/51] hw/arm/raspi: Remove deprecated raspi2/raspi3 aliases Peter Maydell
2021-09-01 10:36 ` [PULL 03/51] hw/intc/arm_gicv3_dist: Rename 64-bit accessors with 'q' suffix Peter Maydell
2021-09-01 10:36 ` [PULL 04/51] hw/intc/arm_gicv3: Replace mis-used MEMTX_* constants by booleans Peter Maydell
2021-09-01 10:36 ` [PULL 05/51] hw: Add compat machines for 6.2 Peter Maydell
2021-09-01 10:36 ` [PULL 06/51] target/arm: Implement MVE VADD (floating-point) Peter Maydell
2021-09-01 10:36 ` [PULL 07/51] target/arm: Implement MVE VSUB, VMUL, VABD, VMAXNM, VMINNM Peter Maydell
2021-09-01 10:36 ` [PULL 08/51] target/arm: Implement MVE VCADD Peter Maydell
2021-09-01 10:36 ` [PULL 09/51] target/arm: Implement MVE VFMA and VFMS Peter Maydell
2021-09-01 10:36 ` [PULL 10/51] target/arm: Implement MVE VCMUL and VCMLA Peter Maydell
2021-09-01 10:36 ` [PULL 11/51] target/arm: Implement MVE VMAXNMA and VMINNMA Peter Maydell
2021-09-01 10:36 ` [PULL 12/51] target/arm: Implement MVE scalar fp insns Peter Maydell
2021-09-01 10:36 ` [PULL 13/51] target/arm: Implement MVE fp-with-scalar VFMA, VFMAS Peter Maydell
2021-09-01 10:36 ` [PULL 14/51] softfloat: Remove assertion preventing silencing of NaN in default-NaN mode Peter Maydell
2021-09-01 10:36 ` [PULL 15/51] target/arm: Implement MVE FP max/min across vector Peter Maydell
2021-09-01 10:36 ` [PULL 16/51] target/arm: Implement MVE fp vector comparisons Peter Maydell
2021-09-01 10:36 ` Peter Maydell [this message]
2021-09-01 10:36 ` [PULL 18/51] target/arm: Implement MVE VCVT between floating and fixed point Peter Maydell
2021-09-01 10:36 ` [PULL 19/51] target/arm: Implement MVE VCVT between fp and integer Peter Maydell
2021-09-01 10:36 ` [PULL 20/51] target/arm: Implement MVE VCVT with specified rounding mode Peter Maydell
2021-09-01 10:36 ` [PULL 21/51] target/arm: Implement MVE VCVT between single and half precision Peter Maydell
2021-09-01 10:36 ` [PULL 22/51] target/arm: Implement MVE VRINT insns Peter Maydell
2021-09-01 10:36 ` [PULL 23/51] target/arm: Enable MVE in Cortex-M55 Peter Maydell
2021-09-01 10:36 ` [PULL 24/51] target-arm: Add support for Fujitsu A64FX Peter Maydell
2021-09-01 10:36 ` [PULL 25/51] hw/arm/virt: target-arm: Add A64FX processor support to virt machine Peter Maydell
2021-09-01 10:36 ` [PULL 26/51] tests/arm-cpu-features: Add A64FX processor related tests Peter Maydell
2021-09-01 10:36 ` [PULL 27/51] arm: Move M-profile RAS register block into its own device Peter Maydell
2021-09-01 10:36 ` [PULL 28/51] arm: Move systick device creation from NVIC to ARMv7M object Peter Maydell
2021-09-01 10:36 ` [PULL 29/51] arm: Move system PPB container handling to armv7m Peter Maydell
2021-09-01 10:36 ` [PULL 30/51] hw/timer/armv7m_systick: Add usual QEMU interface comment Peter Maydell
2021-09-01 10:36 ` [PULL 31/51] hw/timer/armv7m_systick: Add input clocks Peter Maydell
2021-09-01 10:36 ` [PULL 32/51] hw/arm/armv7m: Create " Peter Maydell
2021-09-01 10:36 ` [PULL 33/51] armsse: Wire up systick cpuclk clock Peter Maydell
2021-09-01 10:36 ` [PULL 34/51] hw/arm/mps2.c: Connect up armv7m clocks Peter Maydell
2021-09-01 10:36 ` [PULL 35/51] clock: Provide builtin multiplier/divider Peter Maydell
2021-09-01 10:36 ` [PULL 36/51] hw/arm: Don't allocate separate MemoryRegions in stm32 SoC realize Peter Maydell
2021-09-01 10:36 ` [PULL 37/51] hw/arm/stm32f100: Wire up sysclk and refclk Peter Maydell
2021-09-01 10:36 ` [PULL 38/51] hw/arm/stm32f205: " Peter Maydell
2021-09-01 10:36 ` [PULL 39/51] hw/arm/stm32f405: " Peter Maydell
2021-09-01 10:36 ` [PULL 40/51] hw/arm/stm32vldiscovery: Delete trailing blank line Peter Maydell
2021-09-01 10:36 ` [PULL 41/51] hw/arm/nrf51: Wire up sysclk Peter Maydell
2021-09-01 10:36 ` [PULL 42/51] hw/arm/stellaris: split stellaris_sys_init() Peter Maydell
2021-09-01 10:36 ` [PULL 43/51] hw/arm/stellaris: Wire sysclk up to armv7m Peter Maydell
2021-09-01 10:36 ` [PULL 44/51] hw/arm/msf2_soc: Don't allocate separate MemoryRegions Peter Maydell
2021-09-01 10:36 ` [PULL 45/51] hw/arm/msf2: Use Clock input to MSF2_SOC instead of m3clk property Peter Maydell
2021-09-01 10:36 ` [PULL 46/51] hw/arm/msf2-soc: Wire up refclk Peter Maydell
2021-09-01 10:36 ` [PULL 47/51] hw/timer/armv7m_systick: Use clock inputs instead of system_clock_scale Peter Maydell
2021-09-01 10:36 ` [PULL 48/51] hw/arm/stellaris: Fix code style issues in GPTM code Peter Maydell
2021-09-01 10:36 ` [PULL 49/51] hw/arm/stellaris: Split stellaris-gptm into its own file Peter Maydell
2021-09-01 10:36 ` [PULL 50/51] hw/timer/stellaris-gptm: Use Clock input instead of system_clock_scale Peter Maydell
2021-09-01 10:36 ` [PULL 51/51] arm: Remove system_clock_scale global Peter Maydell
2021-09-02 7:48 ` [PULL 00/51] target-arm queue Peter Maydell
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