[RFC PATCH 4/4] arm64: dts: renesas: falcon-cpu: add SPI flash via RPC

[Wolfram Sang <wsa+renesas@sang-engineering.com>]

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Comments: The BSP used 40 MHz as the spi-max-frequency. But it is the
same SPI flash chip as on other R-Car Gen3 boards, so I took the max
value from there, 50MHz. It worked so far.

Probably the boot partition could be described more precisely and split
up into further partitions. Do we want that? So far, I kept what the BSP
is using.

 .../boot/dts/renesas/r8a779a0-falcon-cpu.dtsi | 33 +++++++++++++++++++
 1 file changed, 33 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
index a0a1a1da0d87..854bd7b94ce7 100644
--- a/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779a0-falcon-cpu.dtsi
@@ -166,6 +166,11 @@ mmc_pins: mmc {
 		power-source = <1800>;
 	};
 
+	qspi0_pins: qspi0 {
+		groups = "qspi0_ctrl", "qspi0_data4";
+		function = "qspi0";
+	};
+
 	scif0_pins: scif0 {
 		groups = "scif0_data", "scif0_ctrl";
 		function = "scif0";
@@ -177,6 +182,34 @@ scif_clk_pins: scif_clk {
 	};
 };
 
+&rpc {
+	pinctrl-0 = <&qspi0_pins>;
+	pinctrl-names = "default";
+
+	status = "okay";
+
+	flash@0 {
+		compatible = "spansion,s25fs512s", "jedec,spi-nor";
+		reg = <0>;
+		spi-max-frequency = <50000000>;
+		spi-rx-bus-width = <4>;
+
+		partitions {
+			compatible = "fixed-partitions";
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			boot_partition@0 {
+				reg = <0x00000000 0xc40000>;
+				read-only;
+			};
+			user@00c40000 {
+				reg = <0x00c40000 0x33c0000>;
+			};
+		};
+	};
+};
+
 &rwdt {
 	timeout-sec = <60>;
 	status = "okay";
-- 
2.30.2