From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AFA23C433EF for ; Wed, 27 Oct 2021 06:22:30 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3C4D760F38 for ; Wed, 27 Oct 2021 06:22:30 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3C4D760F38 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2699989CE2; Wed, 27 Oct 2021 06:22:27 +0000 (UTC) Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0AEA889CE2; Wed, 27 Oct 2021 06:22:25 +0000 (UTC) X-IronPort-AV: E=McAfee;i="6200,9189,10149"; a="293547282" X-IronPort-AV: E=Sophos;i="5.87,186,1631602800"; d="scan'208";a="293547282" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2021 23:22:25 -0700 X-IronPort-AV: E=Sophos;i="5.87,186,1631602800"; d="scan'208";a="537409953" Received: from dzhang-mobl2.amr.corp.intel.com (HELO ldmartin-desk2) ([10.251.142.134]) by fmsmga008-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2021 23:22:23 -0700 Date: Tue, 26 Oct 2021 23:22:19 -0700 From: Lucas De Marchi To: Matt Roper Cc: intel-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, Paulo Zanoni , Tvrtko Ursulin , Radhakrishna Sripada Subject: Re: [Intel-gfx] [PATCH 01/11] drm/i915: rework some irq functions to take intel_gt as argument Message-ID: <20211027062219.ey3gydc2qfcstw6q@ldmartin-desk2> X-Patchwork-Hint: comment References: <20211008215635.2026385-1-matthew.d.roper@intel.com> <20211008215635.2026385-2-matthew.d.roper@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii; format=flowed Content-Disposition: inline In-Reply-To: <20211008215635.2026385-2-matthew.d.roper@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" On Fri, Oct 08, 2021 at 02:56:25PM -0700, Matt Roper wrote: >From: Paulo Zanoni > >We'll be adding multi-tile support soon; on multi-tile platforms >interrupts are per-tile and every tile has the full set of >interrupt registers. > >In this commit we start passing intel_gt instead of dev_priv for the >functions that are related to Xe_HP irq handling. Right now we're still >passing tile 0 everywhere, but in later patches we'll start actually >passing the correct tile. > >Signed-off-by: Paulo Zanoni >Co-authored-by: Tvrtko Ursulin >Signed-off-by: Tvrtko Ursulin >Signed-off-by: Radhakrishna Sripada >Signed-off-by: Matt Roper mostly replacing the i915->uncore with the gt->uncore, which right now should be the same. The other changes are just changing Reviewed-by: Lucas De Marchi Lucas De Marchi