From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9823C4332F for ; Sat, 13 Nov 2021 04:36:47 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9283D61105 for ; Sat, 13 Nov 2021 04:36:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235370AbhKMEjh (ORCPT ); Fri, 12 Nov 2021 23:39:37 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:42078 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230185AbhKMEjf (ORCPT ); Fri, 12 Nov 2021 23:39:35 -0500 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AD4aclm008317; Fri, 12 Nov 2021 22:36:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1636778198; bh=f8LgJZNnJCqu2PSnY9a5BSValDnYokfnws05hp1+1AY=; h=From:To:CC:Subject:Date; b=ZvkPdtjYzbGwzGyrL1FcE9KXymkCNcA0GR4s47Yp+Hv124/rxTAPqQCqwFotbZ+Je Ys04A6FD7cyYx5DB9vxbO8UWq1kbFU1Mi9tIqcZ2at9vQPrLGYqNSv2+pIjsyszWQ9 TZBcFJbUJZXDs7p0E/2CXnsfudYbnmtxo++n+rTI= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AD4acbg088877 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 12 Nov 2021 22:36:38 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 12 Nov 2021 22:36:38 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 12 Nov 2021 22:36:37 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AD4abM7045449; Fri, 12 Nov 2021 22:36:37 -0600 From: Nishanth Menon To: Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , , Peng Fan Subject: [PATCH] arm64: dts: ti: k3-am642: Fix the L2 cache sets Date: Fri, 12 Nov 2021 22:36:35 -0600 Message-ID: <20211113043635.4296-1-nm@ti.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi index e2b397c88401..8a76f4821b11 100644 --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi @@ -60,6 +60,6 @@ L2_0: l2-cache0 { cache-level = <2>; cache-size = <0x40000>; cache-line-size = <64>; - cache-sets = <512>; + cache-sets = <256>; }; }; -- 2.32.0 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9226AC433F5 for ; Sat, 13 Nov 2021 04:37:55 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 5B7B561077 for ; Sat, 13 Nov 2021 04:37:55 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 5B7B561077 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:Subject:CC :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=cnxUIqmXbEYv0I881lgKbmZ8gIOavzmGyjq57XTsyl0=; b=gaTywyC9flVoEE 03V1aMY6X2q++sroDSIcLE0ymqgjbr1Pqa4UByvVM9TAYHrqKP70UycNJ6jKonXM4PjNvFNIDzHdn 52lL0xpW7MnQlmh2tV0h9y5aP/+jVPsRso0Y2fS5MJqjydxMcnJ1QBco+CxBZadgRZyM8Oukyvlqs Ca7UaJGKATZLb+zjP8TiU8WpFLHgRdUCv4xIbNKWKpAeXfd4BeBXJqqdtXavi2Gv+dLeO/AM62zxi O28CxtXVuqKa+jkSp5MtyVcyCa9QKPGUjn4XjiUUOvhb56F0QVO7v19xsLQkrHaUGFy4sY1q7XHx7 TVvsit3u700sJN0eHzrg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mlkmR-00CB7G-S3; Sat, 13 Nov 2021 04:36:44 +0000 Received: from fllv0015.ext.ti.com ([198.47.19.141]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1mlkmN-00CB6c-JF for linux-arm-kernel@lists.infradead.org; Sat, 13 Nov 2021 04:36:41 +0000 Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 1AD4aclm008317; Fri, 12 Nov 2021 22:36:38 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1636778198; bh=f8LgJZNnJCqu2PSnY9a5BSValDnYokfnws05hp1+1AY=; h=From:To:CC:Subject:Date; b=ZvkPdtjYzbGwzGyrL1FcE9KXymkCNcA0GR4s47Yp+Hv124/rxTAPqQCqwFotbZ+Je Ys04A6FD7cyYx5DB9vxbO8UWq1kbFU1Mi9tIqcZ2at9vQPrLGYqNSv2+pIjsyszWQ9 TZBcFJbUJZXDs7p0E/2CXnsfudYbnmtxo++n+rTI= Received: from DLEE114.ent.ti.com (dlee114.ent.ti.com [157.170.170.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 1AD4acbg088877 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 12 Nov 2021 22:36:38 -0600 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE114.ent.ti.com (157.170.170.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14; Fri, 12 Nov 2021 22:36:38 -0600 Received: from lelv0326.itg.ti.com (10.180.67.84) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.14 via Frontend Transport; Fri, 12 Nov 2021 22:36:37 -0600 Received: from localhost (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0326.itg.ti.com (8.15.2/8.15.2) with ESMTP id 1AD4abM7045449; Fri, 12 Nov 2021 22:36:37 -0600 From: Nishanth Menon To: Rob Herring , Tero Kristo , Vignesh Raghavendra CC: , , , Nishanth Menon , , Peng Fan Subject: [PATCH] arm64: dts: ti: k3-am642: Fix the L2 cache sets Date: Fri, 12 Nov 2021 22:36:35 -0600 Message-ID: <20211113043635.4296-1-nm@ti.com> X-Mailer: git-send-email 2.32.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211112_203639_702264_DCA67D46 X-CRM114-Status: GOOD ( 10.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org A53's L2 cache[1] on AM642[2] is 256KB. A53's L2 is fixed line length of 64 bytes and 16-way set-associative cache structure. 256KB of L2 / 64 (line length) = 4096 ways 4096 ways / 16 = 256 sets Fix the l2 cache-sets. [1] https://developer.arm.com/documentation/ddi0500/j/Level-2-Memory-System/About-the-L2-memory-system?lang=en [2] https://www.ti.com/lit/pdf/spruim2 Fixes: 8abae9389bdb ("arm64: dts: ti: Add support for AM642 SoC") Reported-by: Peng Fan Signed-off-by: Nishanth Menon --- arch/arm64/boot/dts/ti/k3-am642.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/ti/k3-am642.dtsi b/arch/arm64/boot/dts/ti/k3-am642.dtsi index e2b397c88401..8a76f4821b11 100644 --- a/arch/arm64/boot/dts/ti/k3-am642.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am642.dtsi @@ -60,6 +60,6 @@ L2_0: l2-cache0 { cache-level = <2>; cache-size = <0x40000>; cache-line-size = <64>; - cache-sets = <512>; + cache-sets = <256>; }; }; -- 2.32.0 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel