Re: [PATCH u-boot-marvell 02/10] arm: mvebu: a38x: serdes: Move non-serdes PCIe code to pci_mvebu.c

["Pali Rohár" <pali@kernel.org>]

Hello!

On Monday 29 November 2021 10:22:58 Stefan Roese wrote:
> On 11/29/21 10:06, Pali Rohár wrote:
> 
> <snip>
> 
> > > > After this DTS change, pci-mvebu.c will just replace value of current
> > > > number of lanes (which is set to 4 by serdes code) to value from DTS,
> > > > which is 4. Therefore there should be no change.
> > > > 
> > > > Could you test whole patch series with above DTS change if it works
> > > > properly on Theadorable board?
> > > 
> > > Yes, I don't see any issues with this patchset applied plus this DT
> > > patch on theadorable. The PCIe links are up and with the correct width.
> > > 
> > > What I'm wondering is, when exactly does the PCIe RP start the link
> > > establishment. In my case with AXP this is still in the AXP serdes code
> > > of course. But in the A38x code, it should be in the PCIe controller
> > > driver now AFAIU. I see that you configure the link width in the
> > > controller and do some other configuration (address windows etc), but
> > > at the end you "simply" wait for the link to come up via
> > > mvebu_pcie_wait_for_link(). I would have expected here some special
> > > command (config bit?) to the PCIe controller to start the link
> > > establishment. So when exactly does the A38x start this action?
> > 
> > That is interesting question... While I'm reading it again, I really do
> > not know. Because you are right that mvebu_pcie_wait_for_link() is just
> > waiting for a link and it "magically" comes up. I have tested it on A385
> > and it is stable with different Compex Atheros cards which caused issues
> > in past also on A3720.
> 
> I would prefer, to fully understand when exactly the link establishment
> is started. Since this is crucial for the setup of the controller that
> needs to be done *before* the link starts to come up.

I try to dig as more information as possible and finally I find out that
important information is available also in now removed, but originally
public A38x documentation. Thankfully web archive has copy of it:

https://web.archive.org/web/20200420191927/https://www.marvell.com/content/dam/marvell/en/public-collateral/embedded-processors/marvell-embedded-processors-armada-38x-functional-specifications-2015-11.pdf

  17.3 Link Initialization

  In case the initialization fails and no link is established, the PHY
  will keep on trying to initiate a link forever unless the port is
  disabled. As long as the port is enabled, the PHY will continue trying
  to establish a link; once the PHY identifies that a device is
  connected to it, a link will be established.

PCIe port is enabled by bits in SoC Control 1 Register, which is done in
U-Boot SerDes initialization code. This is IIRC SoC specific, and reason
why every Armada SoC has own SerDes init code.

And looks like that due to "the PHY will keep on trying to initiate a
link forever", the PCIe link comes up when pci-mvebu.c sets all required
registers to correct values. E.g. set correct mode (RC vs endpoint),
link width (x1 vs x4), etc...

> Could you perhaps try to remove some of the register configurations in
> the MVEBU PCIe driver to see, if the link establishment relies on this
> register to be written to (e.g. PCI_EXP_LNKCAP)?

First port on A385 is by default set to X4 width, other ports to X1
width. Without updating LNKCAP to correct width, card in first PCIe port
never initialize. And cards in other ports are initialized even before
pci-mvebu.c starts configuration.

So seems that this matches above behavior. SerDes init code enabled all
PCIe ports. Ports which are using default configuration (second, third)
are immediately initialized and link is established. Port which requires
additional configuration (first port, for switching from X4 to X1) just
stay in that "keep on trying to initiate a link forever" state until
pci-mvebu starts and set PCI_EXP_LNKCAP register, after which PHY try X1
width and success. And seems that this is the reason why 100ms timeout
is needed... As at this stage when pci-mvebu.c switches X4 to X1, init
timeout as defined in PCIe spec (that 100ms) starts ticking. For other
ports it starts ticking when serdes init code enables ports.


I have looked into all PCIe registers which are present in functional
spec, but it looks like that there is no pci-mvebu register which can
turn of LTSSM and link training, like it is in other PCIe controllers.
It looks like that only SoC-specific port enable bits are there.

It is starting to be bigger mess as before... Any suggestion how to
continue with it?

We cannot (easily) move that code which flips PCIe bits in SoC Control 1
Register from SerDes init code to pci-mvebu.c as this is outside of
pci-mvebu.c address space and also it is different on every SoC.
pci-mvebu.c registers are same on all Marvell SoCs, starting from Orion
up to the A39x.

> Thanks,
> Stefan