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From: Ben Widawsky <ben.widawsky@intel.com>
To: linux-cxl@vger.kernel.org
Cc: patches@lists.linux.dev, Ben Widawsky <ben.widawsky@intel.com>,
	Alison Schofield <alison.schofield@intel.com>,
	Dan Williams <dan.j.williams@intel.com>,
	Ira Weiny <ira.weiny@intel.com>,
	Jonathan Cameron <Jonathan.Cameron@Huawei.com>,
	Vishal Verma <vishal.l.verma@intel.com>
Subject: [PATCH 3/4] cxl/core: Extract IW/IG decoding
Date: Thu, 27 Jan 2022 13:29:10 -0800	[thread overview]
Message-ID: <20220127212911.127741-4-ben.widawsky@intel.com> (raw)
In-Reply-To: <20220127212911.127741-1-ben.widawsky@intel.com>

Interleave granularity and ways have specification defined encodings.
Extracting this functionality into the common header file allows other
consumers to make use of it.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>

---

I'm in favor of making these helps part of UABI. Having userspace and
kernel disagree (because of differing spec versions for example) would
be difficult to manage.

Thoughts?
---
 drivers/cxl/core/hdm.c | 11 ++---------
 drivers/cxl/cxl.h      | 17 +++++++++++++++++
 2 files changed, 19 insertions(+), 9 deletions(-)

diff --git a/drivers/cxl/core/hdm.c b/drivers/cxl/core/hdm.c
index 4955ba16c9c8..a28369f264da 100644
--- a/drivers/cxl/core/hdm.c
+++ b/drivers/cxl/core/hdm.c
@@ -133,21 +133,14 @@ static int to_interleave_granularity(u32 ctrl)
 {
 	int val = FIELD_GET(CXL_HDM_DECODER0_CTRL_IG_MASK, ctrl);
 
-	return 256 << val;
+	return cxl_to_interleave_granularity(val);
 }
 
 static int to_interleave_ways(u32 ctrl)
 {
 	int val = FIELD_GET(CXL_HDM_DECODER0_CTRL_IW_MASK, ctrl);
 
-	switch (val) {
-	case 0 ... 4:
-		return 1 << val;
-	case 8 ... 10:
-		return 3 << (val - 8);
-	default:
-		return 0;
-	}
+	return cxl_to_interleave_ways(val);
 }
 
 static int init_hdm_decoder(struct cxl_port *port, struct cxl_decoder *cxld,
diff --git a/drivers/cxl/cxl.h b/drivers/cxl/cxl.h
index 962629c5775f..13fb06849199 100644
--- a/drivers/cxl/cxl.h
+++ b/drivers/cxl/cxl.h
@@ -64,6 +64,23 @@ static inline int cxl_hdm_decoder_count(u32 cap_hdr)
 	return val ? val * 2 : 1;
 }
 
+static inline int cxl_to_interleave_granularity(u16 ig)
+{
+	return 256 << ig;
+}
+
+static inline int cxl_to_interleave_ways(u8 eniw)
+{
+	switch (eniw) {
+	case 0 ... 4:
+		return 1 << eniw;
+	case 8 ... 10:
+		return 3 << (eniw - 8);
+	default:
+		return 0;
+	}
+}
+
 /* CXL 2.0 8.2.8.1 Device Capabilities Array Register */
 #define CXLDEV_CAP_ARRAY_OFFSET 0x0
 #define   CXLDEV_CAP_ARRAY_CAP_ID 0
-- 
2.35.0


  parent reply	other threads:[~2022-01-27 21:29 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-27 21:29 [PATCH 0/4] Unify meaning of interleave attributes Ben Widawsky
2022-01-27 21:29 ` [PATCH 1/4] cxl/acpi: Store interleave granularity absolutely Ben Widawsky
2022-01-27 22:46   ` Dan Williams
2022-01-27 21:29 ` [PATCH 2/4] cxl/core: Add more decoder attributes to sysfs Ben Widawsky
2022-01-27 22:45   ` Dan Williams
2022-01-27 21:29 ` Ben Widawsky [this message]
2022-01-27 23:01   ` [PATCH 3/4] cxl/core: Extract IW/IG decoding Dan Williams
2022-01-27 21:29 ` [PATCH 4/4] cxl/acpi: Use common " Ben Widawsky
2022-01-28 10:15 ` [PATCH 0/4] Unify meaning of interleave attributes Jonathan Cameron

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