From: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
To: "Andy Gross" <agross@kernel.org>,
"Bjorn Andersson" <bjorn.andersson@linaro.org>,
"Stanimir Varbanov" <svarbanov@mm-sol.com>,
"Lorenzo Pieralisi" <lorenzo.pieralisi@arm.com>,
"Rob Herring" <robh+dt@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Michael Turquette" <mturquette@baylibre.com>,
"Stephen Boyd" <swboyd@chromium.org>
Cc: Bjorn Helgaas <bhelgaas@google.com>,
Prasad Malisetty <pmaliset@codeaurora.org>,
Vinod Koul <vkoul@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org,
linux-clk@vger.kernel.org, devicetree@vger.kernel.org,
Rob Herring <robh@kernel.org>
Subject: [PATCH v2 02/11] dt-bindings: pci: qcom: Document PCIe bindings for SM8450
Date: Fri, 4 Feb 2022 17:46:36 +0300 [thread overview]
Message-ID: <20220204144645.3016603-3-dmitry.baryshkov@linaro.org> (raw)
In-Reply-To: <20220204144645.3016603-1-dmitry.baryshkov@linaro.org>
Document the PCIe DT bindings for SM8450 SoC. The PCIe IP is similar
to the one used on SM8250, however unlike SM8250, PCIe0 and PCIe1 use
different set of clocks, so two compatible entries are required.
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
---
.../devicetree/bindings/pci/qcom,pcie.txt | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie.txt b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
index da08f0f9de96..65a1fa74e4eb 100644
--- a/Documentation/devicetree/bindings/pci/qcom,pcie.txt
+++ b/Documentation/devicetree/bindings/pci/qcom,pcie.txt
@@ -15,6 +15,8 @@
- "qcom,pcie-sc8180x" for sc8180x
- "qcom,pcie-sdm845" for sdm845
- "qcom,pcie-sm8250" for sm8250
+ - "qcom,pcie-sm8450-pcie0" for PCIe0 on sm8450
+ - "qcom,pcie-sm8450-pcie1" for PCIe1 on sm8450
- "qcom,pcie-ipq6018" for ipq6018
- reg:
@@ -167,6 +169,20 @@
- "tbu" PCIe TBU clock
- "ddrss_sf_tbu" PCIe SF TBU clock
+- clock-names:
+ Usage: required for sm8450-pcie0 and sm8450-pcie1
+ Value type: <stringlist>
+ Definition: Should contain the following entries
+ - "aux" Auxiliary clock
+ - "cfg" Configuration clock
+ - "bus_master" Master AXI clock
+ - "bus_slave" Slave AXI clock
+ - "slave_q2a" Slave Q2A clock
+ - "tbu" PCIe TBU clock
+ - "ddrss_sf_tbu" PCIe SF TBU clock
+ - "aggre0" Aggre NoC PCIe0 AXI clock, only for sm8450-pcie0
+ - "aggre1" Aggre NoC PCIe1 AXI clock
+
- resets:
Usage: required
Value type: <prop-encoded-array>
@@ -244,7 +260,7 @@
- "ahb" AHB reset
- reset-names:
- Usage: required for sc8180x, sdm845 and sm8250
+ Usage: required for sc8180x, sdm845, sm8250 and sm8450
Value type: <stringlist>
Definition: Should contain the following entries
- "pci" PCIe core reset
--
2.34.1
next prev parent reply other threads:[~2022-02-04 14:46 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-04 14:46 [PATCH v2 00/11] PCI: qcom: add support for PCIe on SM8450 platform Dmitry Baryshkov
2022-02-04 14:46 ` [PATCH v2 01/11] dt-bindings: pci: qcom,pcie: drop unused "pipe" clocks Dmitry Baryshkov
2022-02-09 22:22 ` Rob Herring
2022-02-04 14:46 ` Dmitry Baryshkov [this message]
2022-02-04 14:46 ` [PATCH v2 03/11] clk: qcom: gdsc: add support for clocks tied to the GDSC Dmitry Baryshkov
2022-02-04 22:05 ` Bjorn Andersson
2022-02-09 22:41 ` Dmitry Baryshkov
2022-02-11 19:52 ` Dmitry Baryshkov
2022-02-15 10:24 ` Prasad Malisetty (Temp) (QUIC)
2022-02-25 1:55 ` Dmitry Baryshkov
2022-03-01 6:42 ` Prasad Malisetty
2022-03-01 6:47 ` Dmitry Baryshkov
2022-03-01 17:43 ` Bjorn Andersson
2022-02-04 14:46 ` [PATCH v2 04/11] clk: qcom: gcc-sc7280: switch PCIe GDSCs to pipe_clk_gdsc Dmitry Baryshkov
2022-02-04 14:46 ` [PATCH v2 05/11] clk: qcom: gcc-sm8450: " Dmitry Baryshkov
2022-02-04 21:02 ` kernel test robot
2022-02-04 21:02 ` kernel test robot
2022-02-04 14:46 ` [PATCH v2 06/11] PCI: qcom: Balance pm_runtime_foo() calls Dmitry Baryshkov
2022-02-04 14:46 ` [PATCH v2 07/11] PCI: qcom: Remove unnecessary pipe_clk handling Dmitry Baryshkov
2022-02-04 14:46 ` [PATCH v2 08/11] PCI: qcom: Remove pipe_clk_src reparenting Dmitry Baryshkov
2022-02-04 14:46 ` [PATCH v2 09/11] PCI: qcom: Remove redundancy between qcom_pcie and qcom_pcie_cfg Dmitry Baryshkov
2022-02-04 14:46 ` [PATCH v2 10/11] PCI: qcom: Add ddrss_sf_tbu flag Dmitry Baryshkov
2022-02-04 14:46 ` [PATCH v2 11/11] PCI: qcom: Add SM8450 PCIe support Dmitry Baryshkov
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20220204144645.3016603-3-dmitry.baryshkov@linaro.org \
--to=dmitry.baryshkov@linaro.org \
--cc=agross@kernel.org \
--cc=bhelgaas@google.com \
--cc=bjorn.andersson@linaro.org \
--cc=devicetree@vger.kernel.org \
--cc=kw@linux.com \
--cc=linux-arm-msm@vger.kernel.org \
--cc=linux-clk@vger.kernel.org \
--cc=linux-pci@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=mturquette@baylibre.com \
--cc=pmaliset@codeaurora.org \
--cc=robh+dt@kernel.org \
--cc=robh@kernel.org \
--cc=svarbanov@mm-sol.com \
--cc=swboyd@chromium.org \
--cc=vkoul@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.