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From: Jean Delvare <jdelvare@suse.de>
To: Terry Bowman <Terry.Bowman@amd.com>
Cc: linux@roeck-us.net, linux-watchdog@vger.kernel.org,
	linux-i2c@vger.kernel.org, wsa@kernel.org,
	andy.shevchenko@gmail.com, rafael.j.wysocki@intel.com,
	linux-kernel@vger.kernel.org, wim@linux-watchdog.org,
	rrichter@amd.com, thomas.lendacky@amd.com,
	sudheesh.mavila@amd.com, Nehal-bakulchandra.Shah@amd.com,
	Basavaraj.Natikar@amd.com, Shyam-sundar.S-k@amd.com,
	Mario.Limonciello@amd.com
Subject: Re: [PATCH v4 0/9] i2c: piix4: Replace cd6h/cd7h port I/O accesses with MMIO accesses
Date: Wed, 9 Feb 2022 08:04:10 +0100	[thread overview]
Message-ID: <20220209080410.1e7dddd9@endymion.delvare> (raw)
In-Reply-To: <27e60021-30cb-3b1c-f429-2618bf891e5e@amd.com>

On Tue, 8 Feb 2022 17:03:09 -0600, Terry Bowman wrote:
> On 2/8/22 15:46, Jean Delvare wrote:
> > If so, while there's indeed nothing to be done for the most recent
> > systems where only MMIO access is possible, you may still need to
> > enable MMIO access through legacy I/O if you try to use MMIO on
> > chipsets where both are possible. I'm not sure what exactly where you
> > set the limit. In the last patch you say that 0x51 is the first
> > revision of the family 17h CPUs, but is family 17h the first where MMIO
> > is available, or the first where legacy I/O isn't?
>
> Family 17h, SMBus PCI ID >= 0x51 is the first where cd6h/cd7h port I/O is disabled. 
> If SMBus PCI ID < 0x51 then cd6h/cd7h port I/O is used. 

OK, we are safe then :-)

-- 
Jean Delvare
SUSE L3 Support

      reply	other threads:[~2022-02-09  7:04 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-01-30 18:41 [PATCH v4 0/9] i2c: piix4: Replace cd6h/cd7h port I/O accesses with MMIO accesses Terry Bowman
2022-01-30 18:41 ` [PATCH v4 1/9] kernel/resource: Introduce request_mem_region_muxed() Terry Bowman
2022-01-30 18:41 ` [PATCH v4 2/9] i2c: piix4: Replace hardcoded memory map size with a #define Terry Bowman
2022-01-30 18:41 ` [PATCH v4 3/9] i2c: piix4: Move port I/O region request/release code into functions Terry Bowman
2022-02-08 14:45   ` Jean Delvare
2022-02-08 15:15     ` Terry Bowman
2022-01-30 18:41 ` [PATCH v4 4/9] i2c: piix4: Move SMBus controller base address detect into function Terry Bowman
2022-02-08 15:09   ` Jean Delvare
2022-01-30 18:41 ` [PATCH v4 5/9] i2c: piix4: Move SMBus port selection " Terry Bowman
2022-02-08 15:29   ` Jean Delvare
2022-01-30 18:41 ` [PATCH v4 6/9] i2c: piix4: Add EFCH MMIO support to region request and release Terry Bowman
2022-02-08 15:49   ` Jean Delvare
2022-01-30 18:41 ` [PATCH v4 7/9] i2c: piix4: Add EFCH MMIO support to SMBus base address detect Terry Bowman
2022-01-30 18:41 ` [PATCH v4 8/9] i2c: piix4: Add EFCH MMIO support for SMBus port select Terry Bowman
2022-02-08 16:19   ` Jean Delvare
2022-01-30 18:41 ` [PATCH v4 9/9] i2c: piix4: Enable EFCH MMIO for Family 17h+ Terry Bowman
2022-02-08 16:33   ` Jean Delvare
2022-02-08 20:10     ` Andy Shevchenko
2022-02-08 21:00       ` Terry Bowman
2022-01-31 11:01 ` [PATCH v4 0/9] i2c: piix4: Replace cd6h/cd7h port I/O accesses with MMIO accesses Andy Shevchenko
2022-02-01 15:21   ` Terry Bowman
2022-02-07 12:08 ` Wolfram Sang
2022-02-08 17:11 ` Jean Delvare
2022-02-08 19:36   ` Terry Bowman
2022-02-08 21:46     ` Jean Delvare
2022-02-08 23:03       ` Terry Bowman
2022-02-09  7:04         ` Jean Delvare [this message]

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