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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE
Date: Thu, 21 Apr 2022 12:18:24 +0100	[thread overview]
Message-ID: <20220421111846.2011565-10-peter.maydell@linaro.org> (raw)
In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org>

Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can
delete the device entirely.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220404154658.565020-3-peter.maydell@linaro.org
---
 hw/intc/exynos4210_gic.c | 107 ---------------------------------------
 1 file changed, 107 deletions(-)

diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c
index bc73d1f1152..794f6b5ac72 100644
--- a/hw/intc/exynos4210_gic.c
+++ b/hw/intc/exynos4210_gic.c
@@ -373,110 +373,3 @@ static void exynos4210_gic_register_types(void)
 }
 
 type_init(exynos4210_gic_register_types)
-
-/* IRQ OR Gate struct.
- *
- * This device models an OR gate. There are n_in input qdev gpio lines and one
- * output sysbus IRQ line. The output IRQ level is formed as OR between all
- * gpio inputs.
- */
-
-#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate"
-OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE)
-
-struct Exynos4210IRQGateState {
-    SysBusDevice parent_obj;
-
-    uint32_t n_in;      /* inputs amount */
-    uint32_t *level;    /* input levels */
-    qemu_irq out;       /* output IRQ */
-};
-
-static Property exynos4210_irq_gate_properties[] = {
-    DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1),
-    DEFINE_PROP_END_OF_LIST(),
-};
-
-static const VMStateDescription vmstate_exynos4210_irq_gate = {
-    .name = "exynos4210.irq_gate",
-    .version_id = 2,
-    .minimum_version_id = 2,
-    .fields = (VMStateField[]) {
-        VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_in),
-        VMSTATE_END_OF_LIST()
-    }
-};
-
-/* Process a change in IRQ input. */
-static void exynos4210_irq_gate_handler(void *opaque, int irq, int level)
-{
-    Exynos4210IRQGateState *s = (Exynos4210IRQGateState *)opaque;
-    uint32_t i;
-
-    assert(irq < s->n_in);
-
-    s->level[irq] = level;
-
-    for (i = 0; i < s->n_in; i++) {
-        if (s->level[i] >= 1) {
-            qemu_irq_raise(s->out);
-            return;
-        }
-    }
-
-    qemu_irq_lower(s->out);
-}
-
-static void exynos4210_irq_gate_reset(DeviceState *d)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(d);
-
-    memset(s->level, 0, s->n_in * sizeof(*s->level));
-}
-
-/*
- * IRQ Gate initialization.
- */
-static void exynos4210_irq_gate_init(Object *obj)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(obj);
-    SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
-
-    sysbus_init_irq(sbd, &s->out);
-}
-
-static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp)
-{
-    Exynos4210IRQGateState *s = EXYNOS4210_IRQ_GATE(dev);
-
-    /* Allocate general purpose input signals and connect a handler to each of
-     * them */
-    qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in);
-
-    s->level = g_malloc0(s->n_in * sizeof(*s->level));
-}
-
-static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data)
-{
-    DeviceClass *dc = DEVICE_CLASS(klass);
-
-    dc->reset = exynos4210_irq_gate_reset;
-    dc->vmsd = &vmstate_exynos4210_irq_gate;
-    device_class_set_props(dc, exynos4210_irq_gate_properties);
-    dc->realize = exynos4210_irq_gate_realize;
-}
-
-static const TypeInfo exynos4210_irq_gate_info = {
-    .name          = TYPE_EXYNOS4210_IRQ_GATE,
-    .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(Exynos4210IRQGateState),
-    .instance_init = exynos4210_irq_gate_init,
-    .class_init    = exynos4210_irq_gate_class_init,
-};
-
-static void exynos4210_irq_gate_register_types(void)
-{
-    type_register_static(&exynos4210_irq_gate_info);
-}
-
-type_init(exynos4210_irq_gate_register_types)
-- 
2.25.1



  parent reply	other threads:[~2022-04-21 11:32 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-21 11:18 [PULL 00/31] target-arm queue Peter Maydell
2022-04-21 11:18 ` [PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF Peter Maydell
2022-04-21 11:18 ` [PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding Peter Maydell
2022-04-21 11:18 ` [PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Peter Maydell
2022-04-21 11:18 ` [PULL 04/31] hw/arm: versal: Create an APU CPU Cluster Peter Maydell
2022-04-21 11:18 ` [PULL 05/31] hw/arm: versal: Add the Cortex-R5Fs Peter Maydell
2022-04-21 11:18 ` [PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL Peter Maydell
2022-04-21 11:18 ` [PULL 07/31] hw/arm: versal: Connect the CRL Peter Maydell
2022-04-21 11:18 ` [PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device Peter Maydell
2022-04-21 11:18 ` Peter Maydell [this message]
2022-04-21 11:18 ` [PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table Peter Maydell
2022-04-21 11:18 ` [PULL 13/31] hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] Peter Maydell
2022-04-21 11:18 ` [PULL 14/31] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 15/31] hw/arm/exynos4210: Put external GIC into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 16/31] hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 17/31] hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c Peter Maydell
2022-04-21 11:18 ` [PULL 18/31] hw/arm/exynos4210: Delete unused macro definitions Peter Maydell
2022-04-21 11:18 ` [PULL 19/31] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 20/31] hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines Peter Maydell
2022-04-21 11:18 ` [PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners Peter Maydell
2022-04-21 11:18 ` [PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs Peter Maydell
2022-04-21 11:18 ` [PULL 23/31] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() Peter Maydell
2022-04-21 11:18 ` [PULL 24/31] hw/arm/exynos4210: Put combiners into state struct Peter Maydell
2022-04-21 11:18 ` [PULL 25/31] hw/arm/exynos4210: Drop Exynos4210Irq struct Peter Maydell
2022-04-21 11:18 ` [PULL 26/31] hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' Peter Maydell
2022-04-21 11:18 ` [PULL 27/31] hw/arm/stellaris: " Peter Maydell
2022-04-21 11:18 ` [PULL 28/31] hw/core/irq: remove unused 'qemu_irq_split' function Peter Maydell
2022-04-21 11:18 ` [PULL 29/31] hw/arm/virt: impact of gic-version on max CPUs Peter Maydell
2022-04-21 11:18 ` [PULL 30/31] hw/misc: Add PWRON STRAP bit fields in GCR module Peter Maydell
2022-04-21 11:18 ` [PULL 31/31] hw/arm: Use bit fields for NPCM7XX PWRON STRAPs Peter Maydell
2022-04-21 16:24 ` [PULL 00/31] target-arm queue Richard Henderson

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