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From: Alex Deucher <alexander.deucher@amd.com>
To: <amd-gfx@lists.freedesktop.org>
Cc: Alex Deucher <alexander.deucher@amd.com>
Subject: [PATCH 05/11] drm/amdgpu/discovery: store the number of UMC IPs on the asic
Date: Tue, 26 Apr 2022 14:27:22 -0400	[thread overview]
Message-ID: <20220426182728.3006737-5-alexander.deucher@amd.com> (raw)
In-Reply-To: <20220426182728.3006737-1-alexander.deucher@amd.com>

For chips with IP discovery get this from the table,
hardcode it for older asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 9 +++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       | 2 ++
 2 files changed, 11 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 4a793309c019..233e03f5f072 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1033,6 +1033,9 @@ int amdgpu_discovery_reg_base_init(struct amdgpu_device *adev)
 			    le16_to_cpu(ip->hw_id) == SDMA3_HWID)
 				adev->sdma.num_instances++;
 
+			if (le16_to_cpu(ip->hw_id) == UMC_HWID)
+				adev->gmc.num_umc++;
+
 			for (k = 0; k < num_base_address; k++) {
 				/*
 				 * convert the endianness of base addresses in place,
@@ -1667,6 +1670,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 	case CHIP_VEGA10:
 		vega10_reg_base_init(adev);
 		adev->sdma.num_instances = 2;
+		adev->gmc.num_umc = 4;
 		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 0, 0);
 		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 0, 0);
 		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 0);
@@ -1688,6 +1692,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 	case CHIP_VEGA12:
 		vega10_reg_base_init(adev);
 		adev->sdma.num_instances = 2;
+		adev->gmc.num_umc = 4;
 		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 3, 0);
 		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 3, 0);
 		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 0, 1);
@@ -1710,6 +1715,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 		vega10_reg_base_init(adev);
 		adev->sdma.num_instances = 1;
 		adev->vcn.num_vcn_inst = 1;
+		adev->gmc.num_umc = 2;
 		if (adev->apu_flags & AMD_APU_IS_RAVEN2) {
 			adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 2, 0);
 			adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 2, 0);
@@ -1747,6 +1753,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 	case CHIP_VEGA20:
 		vega20_reg_base_init(adev);
 		adev->sdma.num_instances = 2;
+		adev->gmc.num_umc = 8;
 		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 0);
 		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 0);
 		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 0);
@@ -1770,6 +1777,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 		arct_reg_base_init(adev);
 		adev->sdma.num_instances = 8;
 		adev->vcn.num_vcn_inst = 2;
+		adev->gmc.num_umc = 8;
 		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 1);
 		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 1);
 		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 2, 1);
@@ -1797,6 +1805,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
 		aldebaran_reg_base_init(adev);
 		adev->sdma.num_instances = 5;
 		adev->vcn.num_vcn_inst = 2;
+		adev->gmc.num_umc = 4;
 		adev->ip_versions[MMHUB_HWIP][0] = IP_VERSION(9, 4, 2);
 		adev->ip_versions[ATHUB_HWIP][0] = IP_VERSION(9, 4, 2);
 		adev->ip_versions[OSSSYS_HWIP][0] = IP_VERSION(4, 4, 0);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 67e488cdc816..e7dc069c4512 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -260,6 +260,8 @@ struct amdgpu_gmc {
 
 	/* MALL size */
 	u64 mall_size;
+	/* number of UMC instances */
+	int num_umc;
 };
 
 #define amdgpu_gmc_flush_gpu_tlb(adev, vmid, vmhub, type) ((adev)->gmc.gmc_funcs->flush_gpu_tlb((adev), (vmid), (vmhub), (type)))
-- 
2.35.1


  parent reply	other threads:[~2022-04-26 18:27 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-26 18:27 [PATCH 01/11] drm/amdgpu: update latest IP discovery table structures Alex Deucher
2022-04-26 18:27 ` [PATCH 02/11] drm/amdgpu/discovery: populate additional GC info Alex Deucher
2022-04-26 18:27 ` [PATCH 03/11] drm/amdgpu/discovery: fix byteswapping in gc info parsing Alex Deucher
2022-04-26 18:27 ` [PATCH 04/11] drm/amdgpu: store the mall size in the gmc structure Alex Deucher
2022-04-26 18:27 ` Alex Deucher [this message]
2022-04-26 18:27 ` [PATCH 06/11] drm/amdgpu/discovery: handle UMC harvesting in IP discovery Alex Deucher
2022-04-26 18:27 ` [PATCH 07/11] drm/amdgpu/discovery: add a function to get the mall_size Alex Deucher
2022-04-26 18:27 ` [PATCH 08/11] drm/amdgpu/discovery: add additional validation Alex Deucher
2022-04-26 18:27 ` [PATCH 09/11] drm/amdgpu/discovery: add a function to parse the vcn info table Alex Deucher
2022-04-26 18:27 ` [PATCH 10/11] drm/amdgpu/discovery: move all table parsing into amdgpu_discovery.c Alex Deucher
2022-04-26 18:27 ` [PATCH 11/11] drm/amdkfd: add helper to generate cache info from gfx config Alex Deucher
2022-04-29  2:54   ` Zhang, Hawking
2022-04-27  5:52 ` [PATCH 01/11] drm/amdgpu: update latest IP discovery table structures Christian König

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