From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B943C43217 for ; Wed, 11 May 2022 21:41:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348267AbiEKVls (ORCPT ); Wed, 11 May 2022 17:41:48 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:59824 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1347797AbiEKVln (ORCPT ); Wed, 11 May 2022 17:41:43 -0400 Received: from gloria.sntech.de (gloria.sntech.de [185.11.138.130]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 87EC15C77B; Wed, 11 May 2022 14:41:42 -0700 (PDT) Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nou5O-0005NU-3o; Wed, 11 May 2022 23:41:34 +0200 From: Heiko Stuebner To: palmer@dabbelt.com, paul.walmsley@sifive.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Date: Wed, 11 May 2022 23:41:29 +0200 Message-Id: <20220511214132.2281431-1-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. As Palmer suggested, merging might have to wait until the cache instructions have landed in compilers, but I wanted to put the block-size changes out there for people to look at already and also update the series to match the current svpbmt state. changes in v2: - cbom-block-size is hardware-specific and comes from firmware - update Kconfig name to use the ISA extension name - select the ALTERNATIVES symbol when enabled - shorten the line lengths of the errata-assembly Heiko Stuebner (3): dt-bindings: riscv: document cbom-block-size riscv: Implement Zicbom-based cache management operations riscv: implement cache-management errata for T-Head SoCs .../devicetree/bindings/riscv/cpus.yaml | 7 ++ arch/riscv/Kconfig | 15 +++ arch/riscv/Kconfig.erratas | 10 ++ arch/riscv/errata/thead/errata.c | 5 + arch/riscv/include/asm/cacheflush.h | 6 ++ arch/riscv/include/asm/errata_list.h | 80 +++++++++++++++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 17 ++++ arch/riscv/kernel/setup.c | 2 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/dma-noncoherent.c | 92 +++++++++++++++++++ 12 files changed, 235 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/mm/dma-noncoherent.c -- 2.35.1 From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 4F02CC4332F for ; Wed, 11 May 2022 21:41:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-Id:Date:Subject:Cc :To:From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=d0OhrT1KvYvJHkjjyZfVOOj2LMh0qOZTJ0s0JULqQ10=; b=kYM8m9/qKsvXwM X1V6HIA3Eu0XzoTEeKFlMLMB0wUCALUpz4tb5EBDE4ZlnOpEtqa+BH7Q7YCHrI9wakgSnP2hpweE8 w6YHOX7JjPsvyoH2+al9YAs2JHPc6IQcn2KTE4oGIOSByO4G0ZjN8kt8T+i3ezLj9kPDtWUVhzM5k nSZMCn0WcjxHO+dVbdJ3NAe3MsuOejozcuIFf7xC+Ds/lvhIH7SJ/P+V4h4E0UV3ApV0C2jLuPf6X Zms2g+2d3oZ2vhZoI8UPS6+9VUpSt+zbUggQlQeXmXV9I/iy2JYO40vS1Glo9Gj3+QJNcyqIUt0ji hiXP5st4Bk32CnaGuDSg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1nou5R-008p40-Jv; Wed, 11 May 2022 21:41:37 +0000 Received: from gloria.sntech.de ([185.11.138.130]) by bombadil.infradead.org with esmtps (Exim 4.94.2 #2 (Red Hat Linux)) id 1nou5P-008p34-OW for linux-riscv@lists.infradead.org; Wed, 11 May 2022 21:41:37 +0000 Received: from ip5b412258.dynamic.kabel-deutschland.de ([91.65.34.88] helo=phil.lan) by gloria.sntech.de with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1nou5O-0005NU-3o; Wed, 11 May 2022 23:41:34 +0200 From: Heiko Stuebner To: palmer@dabbelt.com, paul.walmsley@sifive.com Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, mick@ics.forth.gr, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, robh+dt@kernel.org, krzk+dt@kernel.org, devicetree@vger.kernel.org, Heiko Stuebner Subject: [PATCH v2 0/2] riscv: implement Zicbom-based CMO instructions + the t-head variant Date: Wed, 11 May 2022 23:41:29 +0200 Message-Id: <20220511214132.2281431-1-heiko@sntech.de> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220511_144135_824577_A6F290EE X-CRM114-Status: GOOD ( 14.12 ) X-BeenThere: linux-riscv@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-riscv" Errors-To: linux-riscv-bounces+linux-riscv=archiver.kernel.org@lists.infradead.org This series is based on the alternatives changes done in my svpbmt series and thus also depends on Atish's isa-extension parsing series. It implements using the cache-management instructions from the Zicbom- extension to handle cache flush, etc actions on platforms needing them. SoCs using cpu cores from T-Head like the Allwinne D1 implement a different set of cache instructions. But while they are different, instructions they provide the same functionality, so a variant can easly hook into the existing alternatives mechanism on those. As Palmer suggested, merging might have to wait until the cache instructions have landed in compilers, but I wanted to put the block-size changes out there for people to look at already and also update the series to match the current svpbmt state. changes in v2: - cbom-block-size is hardware-specific and comes from firmware - update Kconfig name to use the ISA extension name - select the ALTERNATIVES symbol when enabled - shorten the line lengths of the errata-assembly Heiko Stuebner (3): dt-bindings: riscv: document cbom-block-size riscv: Implement Zicbom-based cache management operations riscv: implement cache-management errata for T-Head SoCs .../devicetree/bindings/riscv/cpus.yaml | 7 ++ arch/riscv/Kconfig | 15 +++ arch/riscv/Kconfig.erratas | 10 ++ arch/riscv/errata/thead/errata.c | 5 + arch/riscv/include/asm/cacheflush.h | 6 ++ arch/riscv/include/asm/errata_list.h | 80 +++++++++++++++- arch/riscv/include/asm/hwcap.h | 1 + arch/riscv/kernel/cpu.c | 1 + arch/riscv/kernel/cpufeature.c | 17 ++++ arch/riscv/kernel/setup.c | 2 + arch/riscv/mm/Makefile | 1 + arch/riscv/mm/dma-noncoherent.c | 92 +++++++++++++++++++ 12 files changed, 235 insertions(+), 2 deletions(-) create mode 100644 arch/riscv/mm/dma-noncoherent.c -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv