[PULL 00/25] target-arm queue

From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 00/25] target-arm queue
Date: Mon, 27 Jun 2022 11:22:11 +0100	[thread overview]
Message-ID: <20220627102236.3097629-1-peter.maydell@linaro.org> (raw)

target-arm queue, mostly SME preliminaries.

In the unlikely event we don't land the rest of SME before freeze
for 7.1 we can revert the docs/property changes included here.

-- PMM

The following changes since commit 097ccbbbaf2681df1e65542e5b7d2b2d0c66e2bc:

  Merge tag 'qemu-sparc-20220626' of https://github.com/mcayland/qemu into staging (2022-06-27 05:21:05 +0530)

are available in the Git repository at:

  https://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20220627

for you to fetch changes up to 59e1b8a22ea9f947d038ccac784de1020f266e14:

  target/arm: Check V7VE as well as LPAE in arm_pamax (2022-06-27 11:18:17 +0100)

----------------------------------------------------------------
target-arm queue:
 * sphinx: change default language to 'en'
 * Diagnose attempts to emulate EL3 in hvf as well as kvm
 * More SME groundwork patches
 * virt: Fix calculation of physical address space size
   for v7VE CPUs (eg cortex-a15)

----------------------------------------------------------------
Alexander Graf (2):
      accel: Introduce current_accel_name()
      target/arm: Catch invalid kvm state also for hvf

Martin Liška (1):
      sphinx: change default language to 'en'

Richard Henderson (22):
      target/arm: Implement TPIDR2_EL0
      target/arm: Add SMEEXC_EL to TB flags
      target/arm: Add syn_smetrap
      target/arm: Add ARM_CP_SME
      target/arm: Add SVCR
      target/arm: Add SMCR_ELx
      target/arm: Add SMIDR_EL1, SMPRI_EL1, SMPRIMAP_EL2
      target/arm: Add PSTATE.{SM,ZA} to TB flags
      target/arm: Add the SME ZA storage to CPUARMState
      target/arm: Implement SMSTART, SMSTOP
      target/arm: Move error for sve%d property to arm_cpu_sve_finalize
      target/arm: Create ARMVQMap
      target/arm: Generalize cpu_arm_{get,set}_vq
      target/arm: Generalize cpu_arm_{get, set}_default_vec_len
      target/arm: Move arm_cpu_*_finalize to internals.h
      target/arm: Unexport aarch64_add_*_properties
      target/arm: Add cpu properties for SME
      target/arm: Introduce sve_vqm1_for_el_sm
      target/arm: Add SVL to TB flags
      target/arm: Move pred_{full, gvec}_reg_{offset, size} to translate-a64.h
      target/arm: Extend arm_pamax to more than aarch64
      target/arm: Check V7VE as well as LPAE in arm_pamax

 docs/conf.py                     |   2 +-
 docs/system/arm/cpu-features.rst |  56 ++++++++++
 include/qemu/accel.h             |   1 +
 target/arm/cpregs.h              |   5 +
 target/arm/cpu.h                 | 103 ++++++++++++++-----
 target/arm/helper-sme.h          |  21 ++++
 target/arm/helper.h              |   1 +
 target/arm/internals.h           |   4 +
 target/arm/syndrome.h            |  14 +++
 target/arm/translate-a64.h       |  38 +++++++
 target/arm/translate.h           |   6 ++
 accel/accel-common.c             |   8 ++
 hw/arm/virt.c                    |  10 +-
 softmmu/vl.c                     |   3 +-
 target/arm/cpu.c                 |  32 ++++--
 target/arm/cpu64.c               | 205 ++++++++++++++++++++++++++++---------
 target/arm/helper.c              | 213 +++++++++++++++++++++++++++++++++++++--
 target/arm/kvm64.c               |   2 +-
 target/arm/machine.c             |  34 +++++++
 target/arm/ptw.c                 |  26 +++--
 target/arm/sme_helper.c          |  61 +++++++++++
 target/arm/translate-a64.c       |  46 +++++++++
 target/arm/translate-sve.c       |  36 -------
 target/arm/meson.build           |   1 +
 24 files changed, 782 insertions(+), 146 deletions(-)
 create mode 100644 target/arm/helper-sme.h
 create mode 100644 target/arm/sme_helper.c