Re: [PATCH v5 2/2] eal: add power mgmt support on Arm

From: Stephen Hemminger <stephen@networkplumber.org>
To: Feifei Wang <feifei.wang2@arm.com>
Cc: Ruifeng Wang <ruifeng.wang@arm.com>,
	dev@dpdk.org, nd@arm.com, David Hunt <david.hunt@intel.com>
Subject: Re: [PATCH v5 2/2] eal: add power mgmt support on Arm
Date: Fri, 17 Feb 2023 08:23:01 -0800	[thread overview]
Message-ID: <20230217082301.644addae@hermes.local> (raw)
In-Reply-To: <20221214081430.1717903-3-feifei.wang2@arm.com>

On Wed, 14 Dec 2022 16:14:30 +0800
Feifei Wang <feifei.wang2@arm.com> wrote:

> +__check_val_size(const uint8_t sz)
> +{
> +	switch (sz) {
> +	case sizeof(uint8_t):  /* fall-through */
> +	case sizeof(uint16_t): /* fall-through */
> +	case sizeof(uint32_t): /* fall-through */
> +	case sizeof(uint64_t): /* fall-through */
> +		return 0;
> +	default:
> +		/* unexpected size */
> +		return -1;
> +	}
> +}
> +#endif

One simplification would be to get rid of this function
and just check for unexpected size in the switch
statement in rte_power_monitor().

> +	switch (pmc->size) {
> +	case sizeof(uint8_t):
> +		__RTE_ARM_LOAD_EXC_8(pmc->addr, cur_value, __ATOMIC_RELAXED);
> +		__RTE_ARM_WFE()
> +		break;
> +	case sizeof(uint16_t):
> +		__RTE_ARM_LOAD_EXC_16(pmc->addr, cur_value, __ATOMIC_RELAXED);
> +		__RTE_ARM_WFE()
> +		break;
> +	case sizeof(uint32_t):
> +		__RTE_ARM_LOAD_EXC_32(pmc->addr, cur_value, __ATOMIC_RELAXED);
> +		__RTE_ARM_WFE()
> +		break;
> +	case sizeof(uint64_t):
> +		__RTE_ARM_LOAD_EXC_64(pmc->addr, cur_value, __ATOMIC_RELAXED);
> +		__RTE_ARM_WFE()

	default:
		return -1; /* unexpected size */
> +	}