diff for duplicates of <2426089.g6yXFYEL1F@jernej-laptop>
diff --git a/a/1.txt b/N1/1.txt
index 50fc6e9..947b6a6 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -1,25 +1,25 @@
Dne ponedeljek, 25. junij 2018 ob 10:14:52 CEST je Chen-Yu Tsai napisal(a):
> On Mon, Jun 25, 2018 at 3:58 PM, Jernej Škrabec
>
-> <jernej.skrabec@gmail.com> wrote:
+> <jernej.skrabec-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai
napisal(a):
> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej Škrabec
> >>
-> >> <jernej.skrabec@gmail.com> wrote:
+> >> <jernej.skrabec-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> wrote:
> >> > Dne četrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej Škrabec
napisal(a):
> >> >> Dne četrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai
napisal(a):
> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej Škrabec
-> >> >> > <jernej.skrabec@siol.net>
+> >> >> > <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
> >> >>
> >> >> wrote:
> >> >> > > Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai
> >
> > napisal(a):
> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej Škrabec
-> >> >> > >> <jernej.skrabec@siol.net>
+> >> >> > >> <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
> >> >> > >
> >> >> > > wrote:
> >> >> > >> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai
@@ -27,7 +27,7 @@ napisal(a):
> >> > napisal(a):
> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej Škrabec
> >> >> > >> >>
-> >> >> > >> >> <jernej.skrabec@siol.net> wrote:
+> >> >> > >> >> <jernej.skrabec-gGgVlfcn5nU@public.gmane.org> wrote:
> >> >> > >> >> > Hi,
> >> >> > >> >> >
> >> >> > >> >> > Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripard
@@ -46,7 +46,7 @@ napisal(a):
> >> >> > >> >> >> >
> >> >> > >> >> >> > Add support for such TCONs.
> >> >> > >> >> >> >
-> >> >> > >> >> >> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
+> >> >> > >> >> >> > Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
> >> >> > >> >> >> > ---
> >> >> > >> >> >> >
> >> >> > >> >> >> > drivers/gpu/drm/sun4i/sun4i_tcon.c | 11 +++++++++++
@@ -377,4 +377,12 @@ is enabled or not? But that's debate for another time.
I will send new R40 HDMI patches according your original proposal.
Best regards,
-Jernej
\ No newline at end of file
+Jernej
+
+
+
+
+--
+You received this message because you are subscribed to the Google Groups "linux-sunxi" group.
+To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org
+For more options, visit https://groups.google.com/d/optout.
\ No newline at end of file
diff --git a/a/content_digest b/N1/content_digest
index 31ea73d..4b231f3 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -8,31 +8,34 @@
"ref\0CAGb2v676mFiOry5eQabzkyVaQ6R64gT2_XuBzTAtHorNzfwCuw\@mail.gmail.com\0"
]
[
- "From\0Jernej \305\240krabec <jernej.skrabec\@gmail.com>\0"
+ "ref\0CAGb2v676mFiOry5eQabzkyVaQ6R64gT2_XuBzTAtHorNzfwCuw-JsoAwUIsXosN+BqQ9rBEUg\@public.gmane.org\0"
]
[
- "Subject\0Re: [linux-sunxi] Re: [PATCH v2 11/27] drm/sun4i: tcon: Add support for tcon-top gate\0"
+ "From\0Jernej \305\240krabec <jernej.skrabec-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org>\0"
+]
+[
+ "Subject\0Re: Re: [PATCH v2 11/27] drm/sun4i: tcon: Add support for tcon-top gate\0"
]
[
"Date\0Mon, 25 Jun 2018 11:10:30 +0200\0"
]
[
- "To\0linux-sunxi\@googlegroups.com",
- " wens\@csie.org\0"
+ "To\0linux-sunxi-/JYPxA39Uh5TLH3MbocFFw\@public.gmane.org",
+ " wens-jdAy2FN1RRM\@public.gmane.org\0"
]
[
- "Cc\0Maxime Ripard <maxime.ripard\@bootlin.com>",
- " Rob Herring <robh+dt\@kernel.org>",
- " David Airlie <airlied\@linux.ie>",
- " Gustavo Padovan <gustavo\@padovan.org>",
- " Maarten Lankhorst <maarten.lankhorst\@linux.intel.com>",
- " Sean Paul <seanpaul\@chromium.org>",
- " Mark Rutland <mark.rutland\@arm.com>",
- " dri-devel <dri-devel\@lists.freedesktop.org>",
- " devicetree <devicetree\@vger.kernel.org>",
- " linux-arm-kernel <linux-arm-kernel\@lists.infradead.org>",
- " linux-kernel <linux-kernel\@vger.kernel.org>",
- " linux-clk <linux-clk\@vger.kernel.org>\0"
+ "Cc\0Maxime Ripard <maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ\@public.gmane.org>",
+ " Rob Herring <robh+dt-DgEjT+Ai2ygdnm+yROfE0A\@public.gmane.org>",
+ " David Airlie <airlied-cv59FeDIM0c\@public.gmane.org>",
+ " Gustavo Padovan <gustavo-THi1TnShQwVAfugRpC6u6w\@public.gmane.org>",
+ " Maarten Lankhorst <maarten.lankhorst-VuQAYsv1563Yd54FQh9/CA\@public.gmane.org>",
+ " Sean Paul <seanpaul-F7+t8E8rja9g9hUCZPvPmw\@public.gmane.org>",
+ " Mark Rutland <mark.rutland-5wv7dgnIgG8\@public.gmane.org>",
+ " dri-devel <dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW\@public.gmane.org>",
+ " devicetree <devicetree-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org>",
+ " linux-arm-kernel <linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r\@public.gmane.org>",
+ " linux-kernel <linux-kernel-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org>",
+ " linux-clk <linux-clk-u79uwXL29TY76Z2rM5mHXA\@public.gmane.org>\0"
]
[
"\0000:1\0"
@@ -44,25 +47,25 @@
"Dne ponedeljek, 25. junij 2018 ob 10:14:52 CEST je Chen-Yu Tsai napisal(a):\n",
"> On Mon, Jun 25, 2018 at 3:58 PM, Jernej \305\240krabec\n",
"> \n",
- "> <jernej.skrabec\@gmail.com> wrote:\n",
+ "> <jernej.skrabec-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org> wrote:\n",
"> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai \n",
"napisal(a):\n",
"> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej \305\240krabec\n",
"> >> \n",
- "> >> <jernej.skrabec\@gmail.com> wrote:\n",
+ "> >> <jernej.skrabec-Re5JQEeQqe8AvxtiuMwx3w\@public.gmane.org> wrote:\n",
"> >> > Dne \304\215etrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej \305\240krabec \n",
"napisal(a):\n",
"> >> >> Dne \304\215etrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai \n",
"napisal(a):\n",
"> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej \305\240krabec\n",
- "> >> >> > <jernej.skrabec\@siol.net>\n",
+ "> >> >> > <jernej.skrabec-gGgVlfcn5nU\@public.gmane.org>\n",
"> >> >> \n",
"> >> >> wrote:\n",
"> >> >> > > Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai\n",
"> > \n",
"> > napisal(a):\n",
"> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej \305\240krabec\n",
- "> >> >> > >> <jernej.skrabec\@siol.net>\n",
+ "> >> >> > >> <jernej.skrabec-gGgVlfcn5nU\@public.gmane.org>\n",
"> >> >> > > \n",
"> >> >> > > wrote:\n",
"> >> >> > >> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai\n",
@@ -70,7 +73,7 @@
"> >> > napisal(a):\n",
"> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej \305\240krabec\n",
"> >> >> > >> >> \n",
- "> >> >> > >> >> <jernej.skrabec\@siol.net> wrote:\n",
+ "> >> >> > >> >> <jernej.skrabec-gGgVlfcn5nU\@public.gmane.org> wrote:\n",
"> >> >> > >> >> > Hi,\n",
"> >> >> > >> >> > \n",
"> >> >> > >> >> > Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripard\n",
@@ -89,7 +92,7 @@
"> >> >> > >> >> >> > \n",
"> >> >> > >> >> >> > Add support for such TCONs.\n",
"> >> >> > >> >> >> > \n",
- "> >> >> > >> >> >> > Signed-off-by: Jernej Skrabec <jernej.skrabec\@siol.net>\n",
+ "> >> >> > >> >> >> > Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU\@public.gmane.org>\n",
"> >> >> > >> >> >> > ---\n",
"> >> >> > >> >> >> > \n",
"> >> >> > >> >> >> > drivers/gpu/drm/sun4i/sun4i_tcon.c | 11 +++++++++++\n",
@@ -420,7 +423,15 @@
"I will send new R40 HDMI patches according your original proposal.\n",
"\n",
"Best regards,\n",
- "Jernej"
+ "Jernej\n",
+ "\n",
+ "\n",
+ "\n",
+ "\n",
+ "-- \n",
+ "You received this message because you are subscribed to the Google Groups \"linux-sunxi\" group.\n",
+ "To unsubscribe from this group and stop receiving emails from it, send an email to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0\@public.gmane.org\n",
+ "For more options, visit https://groups.google.com/d/optout."
]
-ab4963801d28bf994b601f8eab77da38ebc56ea36ea55f1d48afd9251b618839
+59363e9b18a861ca167bb0236a15f8bf94c79df5d927c458607a2f4905abfbe5
diff --git a/a/1.txt b/N2/1.txt
index 50fc6e9..b5953e0 100644
--- a/a/1.txt
+++ b/N2/1.txt
@@ -1,58 +1,61 @@
Dne ponedeljek, 25. junij 2018 ob 10:14:52 CEST je Chen-Yu Tsai napisal(a):
-> On Mon, Jun 25, 2018 at 3:58 PM, Jernej Škrabec
->
+> On Mon, Jun 25, 2018 at 3:58 PM, Jernej =C5=A0krabec
+>=20
> <jernej.skrabec@gmail.com> wrote:
-> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai
+> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai=20
napisal(a):
-> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej Škrabec
-> >>
+> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej =C5=A0krabec
+> >>=20
> >> <jernej.skrabec@gmail.com> wrote:
-> >> > Dne četrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej Škrabec
+> >> > Dne =C4=8Detrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej =C5=A0kr=
+abec=20
napisal(a):
-> >> >> Dne četrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai
+> >> >> Dne =C4=8Detrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai=20
napisal(a):
-> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej Škrabec
+> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej =C5=A0krabec
> >> >> > <jernej.skrabec@siol.net>
-> >> >>
+> >> >>=20
> >> >> wrote:
> >> >> > > Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai
-> >
+> >=20
> > napisal(a):
-> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej Škrabec
+> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej =C5=A0krabec
> >> >> > >> <jernej.skrabec@siol.net>
-> >> >> > >
+> >> >> > >=20
> >> >> > > wrote:
> >> >> > >> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai
-> >> >
+> >> >=20
> >> > napisal(a):
-> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej Škrabec
-> >> >> > >> >>
+> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej =C5=A0krabec
+> >> >> > >> >>=20
> >> >> > >> >> <jernej.skrabec@siol.net> wrote:
> >> >> > >> >> > Hi,
-> >> >> > >> >> >
-> >> >> > >> >> > Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripard
-> >> >>
+> >> >> > >> >> >=20
+> >> >> > >> >> > Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripa=
+rd
+> >> >>=20
> >> >> napisal(a):
> >> >> > >> >> >> Hi,
-> >> >> > >> >> >>
+> >> >> > >> >> >>=20
> >> >> > >> >> >> On Tue, Jun 12, 2018 at 10:00:20PM +0200, Jernej Skrabec
-> >
+> >=20
> > wrote:
-> >> >> > >> >> >> > TV TCONs connected to TCON TOP have to enable additional
+> >> >> > >> >> >> > TV TCONs connected to TCON TOP have to enable addition=
+al
> >> >> > >> >> >> > gate
> >> >> > >> >> >> > in
> >> >> > >> >> >> > order
> >> >> > >> >> >> > to work.
-> >> >> > >> >> >> >
+> >> >> > >> >> >> >=20
> >> >> > >> >> >> > Add support for such TCONs.
-> >> >> > >> >> >> >
+> >> >> > >> >> >> >=20
> >> >> > >> >> >> > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
> >> >> > >> >> >> > ---
-> >> >> > >> >> >> >
+> >> >> > >> >> >> >=20
> >> >> > >> >> >> > drivers/gpu/drm/sun4i/sun4i_tcon.c | 11 +++++++++++
> >> >> > >> >> >> > drivers/gpu/drm/sun4i/sun4i_tcon.h | 4 ++++
> >> >> > >> >> >> > 2 files changed, 15 insertions(+)
-> >> >> > >> >> >> >
+> >> >> > >> >> >> >=20
> >> >> > >> >> >> > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c
> >> >> > >> >> >> > b/drivers/gpu/drm/sun4i/sun4i_tcon.c index
> >> >> > >> >> >> > 08747fc3ee71..0afb5a94a414
@@ -63,16 +66,16 @@ napisal(a):
> >> >> > >> >> >> > sun4i_tcon_init_clocks(struct
> >> >> > >> >> >> > device
> >> >> > >> >> >> > *dev,
-> >> >> > >> >> >> >
+> >> >> > >> >> >> >=20
> >> >> > >> >> >> > dev_err(dev, "Couldn't get the TCON bus
> >> >> > >> >> >> > clock\n");
> >> >> > >> >> >> > return PTR_ERR(tcon->clk);
-> >> >> > >> >> >> >
+> >> >> > >> >> >> > =20
> >> >> > >> >> >> > }
-> >> >> > >> >> >> >
+> >> >> > >> >> >> >=20
> >> >> > >> >> >> > +
> >> >> > >> >> >> > + if (tcon->quirks->has_tcon_top_gate) {
-> >> >> > >> >> >> > + tcon->top_clk = devm_clk_get(dev,
+> >> >> > >> >> >> > + tcon->top_clk =3D devm_clk_get(dev,
> >> >> > >> >> >> > "tcon-top");
> >> >> > >> >> >> > + if (IS_ERR(tcon->top_clk)) {
> >> >> > >> >> >> > + dev_err(dev, "Couldn't get the TCON
@@ -84,20 +87,23 @@ napisal(a):
> >> >> > >> >> >> > + clk_prepare_enable(tcon->top_clk);
> >> >> > >> >> >> > + }
> >> >> > >> >> >> > +
-> >> >> > >> >> >>
-> >> >> > >> >> >> Is it required for the TCON itself to operate, or does the
+> >> >> > >> >> >>=20
+> >> >> > >> >> >> Is it required for the TCON itself to operate, or does t=
+he
> >> >> > >> >> >> TCON
-> >> >> > >> >> >> requires the TCON TOP, which in turn requires that clock to
+> >> >> > >> >> >> requires the TCON TOP, which in turn requires that clock=
+ to
> >> >> > >> >> >> be
> >> >> > >> >> >> functional?
-> >> >> > >> >> >>
-> >> >> > >> >> >> I find it quite odd to have a clock that isn't meant for a
+> >> >> > >> >> >>=20
+> >> >> > >> >> >> I find it quite odd to have a clock that isn't meant for=
+ a
> >> >> > >> >> >> particular
> >> >> > >> >> >> device to actually be wired to another device. I'm not
> >> >> > >> >> >> saying
> >> >> > >> >> >> this
> >> >> > >> >> >> isn't the case, but it would be a first.
-> >> >> > >> >> >
+> >> >> > >> >> >=20
> >> >> > >> >> > Documentation doesn't say much about that gate. I did few
> >> >> > >> >> > tests
> >> >> > >> >> > and
@@ -106,23 +112,27 @@ napisal(a):
> >> >> > >> >> > gate
> >> >> > >> >> > is
> >> >> > >> >> > disabled. However, there is no image, as expected.
-> >> >> > >> >>
+> >> >> > >> >>=20
> >> >> > >> >> The R40 manual does include it in the diagram, on page 504.
> >> >> > >> >> There's
> >> >> > >> >> also
> >> >> > >> >> a
-> >> >> > >> >> mux to select whether the clock comes directly from the CCU or
+> >> >> > >> >> mux to select whether the clock comes directly from the CCU=
+ or
> >> >> > >> >> the
> >> >> > >> >> TV
-> >> >> > >> >> encoder (a feedback mode?). I assume this is the gate you are
+> >> >> > >> >> encoder (a feedback mode?). I assume this is the gate you a=
+re
> >> >> > >> >> referring
> >> >> > >> >> to
-> >> >> > >> >> here, in which case it is not a bus clock, but rather the TCON
+> >> >> > >> >> here, in which case it is not a bus clock, but rather the T=
+CON
> >> >> > >> >> module
> >> >> > >> >> or
> >> >> > >> >> channel clock, strangely routed.
-> >> >> > >> >>
-> >> >> > >> >> > More interestingly, I enabled test pattern directly in TCON
+> >> >> > >> >>=20
+> >> >> > >> >> > More interestingly, I enabled test pattern directly in TC=
+ON
> >> >> > >> >> > to
> >> >> > >> >> > eliminate
> >> >> > >> >> > influence of the mixer. As soon as I disabled that gate,
@@ -133,12 +143,15 @@ napisal(a):
> >> >> > >> >> > influences
> >> >> > >> >> > something
> >> >> > >> >> > inside TCON.
-> >> >> > >> >> >
-> >> >> > >> >> > Another test I did was that I moved enable/disable gate code
+> >> >> > >> >> >=20
+> >> >> > >> >> > Another test I did was that I moved enable/disable gate c=
+ode
> >> >> > >> >> > to
-> >> >> > >> >> > sun4i_tcon_channel_set_status() and it worked just as well.
-> >> >> > >> >> >
-> >> >> > >> >> > I'll ask AW engineer what that gate actually does, but from
+> >> >> > >> >> > sun4i_tcon_channel_set_status() and it worked just as wel=
+l.
+> >> >> > >> >> >=20
+> >> >> > >> >> > I'll ask AW engineer what that gate actually does, but fr=
+om
> >> >> > >> >> > what I
> >> >> > >> >> > saw,
> >> >> > >> >> > I
@@ -156,12 +169,13 @@ napisal(a):
> >> >> > >> >> > doesn't
> >> >> > >> >> > sound
> >> >> > >> >> > right to me for some reason.
-> >> >> > >> >>
+> >> >> > >> >>=20
> >> >> > >> >> If what I said above it true, then yes, the appropriate
> >> >> > >> >> location
> >> >> > >> >> to
> >> >> > >> >> enable
-> >> >> > >> >> it is the TCON driver, but moreover, the representation of the
+> >> >> > >> >> it is the TCON driver, but moreover, the representation of =
+the
> >> >> > >> >> clock
> >> >> > >> >> tree
> >> >> > >> >> should be fixed such that the TCON takes the clock from the
@@ -173,124 +187,138 @@ napisal(a):
> >> >> > >> >> patch,
> >> >> > >> >> but
> >> >> > >> >> you'd add another for all the clock routing.
-> >> >> > >> >
+> >> >> > >> >=20
> >> >> > >> > Can you be more specific? I not sure what you mean here.
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> For clock related properties in the device tree:
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> &tcon_top {
-> >> >> > >>
-> >> >> > >> clocks = <&ccu CLK_BUS_TCON_TOP>,
-> >> >> > >>
+> >> >> > >>=20
+> >> >> > >> clocks =3D <&ccu CLK_BUS_TCON_TOP>,
+> >> >> > >> =20
> >> >> > >> <&ccu CLK_TCON_TV0>,
> >> >> > >> <&tve0>,
> >> >> > >> <&ccu CLK_TCON_TV1>,
> >> >> > >> <&tve1>;
-> >> >> > >>
-> >> >> > >> clock-names = "bus", "tcon-tv0", "tve0", "tcon-tv1", "tve1";
-> >> >> > >> clock-output-names = "tcon-top-tv0", "tcon-top-tv1";
-> >> >> > >>
+> >> >> > >> =20
+> >> >> > >> clock-names =3D "bus", "tcon-tv0", "tve0", "tcon-tv1", "tv=
+e1";
+> >> >> > >> clock-output-names =3D "tcon-top-tv0", "tcon-top-tv1";
+> >> >> > >>=20
> >> >> > >> };
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> &tcon_tv0 {
-> >> >> > >>
-> >> >> > >> clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>'
-> >> >> > >> clock-names = "ahb", "tcon-ch1";
-> >> >> > >>
+> >> >> > >>=20
+> >> >> > >> clocks =3D <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>'
+> >> >> > >> clock-names =3D "ahb", "tcon-ch1";
+> >> >> > >>=20
> >> >> > >> };
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> A diagram would look like:
> >> >> > >> | This part is TCON TOP |
-> >> >> > >>
+> >> >> > >> =20
> >> >> > >> v v
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> CCU CLK_TCON_TV0 --|----\ |
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> | mux ---- gate ----|-- TCON_TV0
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> TVE0 --------------|----/ |
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> And the same goes for TCON_TV1 and TVE1.
-> >> >> > >>
+> >> >> > >>=20
> >> >> > >> The user manual is a bit lacking on how TVE outputs a clock
> >> >> > >> though.
-> >> >> > >
-> >> >> > > I didn't yet received any response on HW details from AW till now,
+> >> >> > >=20
+> >> >> > > I didn't yet received any response on HW details from AW till n=
+ow,
> >> >> > > but I
> >> >> > > would like to post new version of patches soon.
-> >> >> > >
+> >> >> > >=20
> >> >> > > While chaining like you described could be implemented easily, I
> >> >> > > don't
> >> >> > > think it really represents HW as it is. Tests showed that these
> >> >> > > two
> >> >> > > clocks are independent, otherwise register writes/reads wouldn't
> >> >> > > be
-> >> >> > > possible with tcon- top gate disabled. I chose tcon-top bus clock
+> >> >> > > possible with tcon- top gate disabled. I chose tcon-top bus clo=
+ck
> >> >> > > as
> >> >> > > a
> >> >> > > parent becase if it is not enabled, it simply won't work.
-> >> >> >
-> >> >> > AFAIK with the TCONs, even when the TCON channel clock (not the bus
+> >> >> >=20
+> >> >> > AFAIK with the TCONs, even when the TCON channel clock (not the b=
+us
> >> >> > clock)
> >> >> > is disabled, register accesses still work.
-> >> >>
+> >> >>=20
> >> >> You're right, I just tested that.
-> >> >>
+> >> >>=20
> >> >> > I'm saying that the TCON TOP
-> >> >> > gate is downstream from the TCON channel clock in the CCU. These are
+> >> >> > gate is downstream from the TCON channel clock in the CCU. These =
+are
> >> >> > not
> >> >> > related to the TCON bus clock in the CCU, which affects register
> >> >> > access.
-> >> >> >
-> >> >> > Did Allwinner provide any information regarding the hierarchy of the
+> >> >> >=20
+> >> >> > Did Allwinner provide any information regarding the hierarchy of =
+the
> >> >> > clocks?
-> >> >>
+> >> >>=20
> >> >> No reponse for now.
-> >> >>
+> >> >>=20
> >> >> > > However, if everyone feels chaining is the best way to implement
> >> >> > > it,
> >> >> > > I'll
> >> >> > > do it.
-> >> >> >
-> >> >> > I would like to get it right and match actual hardware. My proposal
+> >> >> >=20
+> >> >> > I would like to get it right and match actual hardware. My propos=
+al
> >> >> > is
> >> >> > based on my understanding from the diagrams in the user manual.
-> >> >>
+> >> >>=20
> >> >> So for now, your explanation is the most reasonable. Should we go
> >> >> ahead
> >> >> and
> >> >> implement your idea?
-> >> >>
-> >> >> Please note that H6 has TCON-TOP too, but it has only one LCD TCON and
+> >> >>=20
+> >> >> Please note that H6 has TCON-TOP too, but it has only one LCD TCON =
+and
> >> >> one
> >> >> TV TCON instead of two of each kind. That means we will have hole in
-> >> >> indices (tcon_lcd0 is 1, tcon_tv0 is 3, which is aligned with R40) and
-> >> >> different TCON- TOP binding (no tcon_tv1 channel clock), but setup is
+> >> >> indices (tcon_lcd0 is 1, tcon_tv0 is 3, which is aligned with R40) =
+and
+> >> >> different TCON- TOP binding (no tcon_tv1 channel clock), but setup =
+is
> >> >> exactly the same.
-> >> >
+> >> >=20
> >> > I just noticed issue with this proposal. If we have following clock
> >> > chain
> >> > for HDMI, everythings is ok:
-> >> >
+> >> >=20
> >> > TCON-TV0 -> TCON-TOP-TV0
-> >> >
-> >> > TCON TV sets TCON-TOP-TV0 clock rate, which in turn sets TCON-TV0 clock
+> >> >=20
+> >> > TCON TV sets TCON-TOP-TV0 clock rate, which in turn sets TCON-TV0 cl=
+ock
> >> > and
> >> > everything works.
-> >> >
+> >> >=20
> >> > However, when TVE will be configured, it would look like this:
-> >> >
+> >> >=20
> >> > TVE0 -> TCON-TOP-TV0
-> >> >
+> >> >=20
> >> > TVE driver will set TVE0 clock to 216 MHz and TCON TV would set
-> >> > TCON-TOP-TV0 rate which in turn sets TVE0 clock to something like 13.5
-> >> > MHz (or whatever is the right clock rate for PAL and NTSC). As you can
-> >> > see, same clock is set to two different rates by two different drivers.
-> >> >
+> >> > TCON-TOP-TV0 rate which in turn sets TVE0 clock to something like 13=
+=2E5
+> >> > MHz (or whatever is the right clock rate for PAL and NTSC). As you c=
+an
+> >> > see, same clock is set to two different rates by two different drive=
+rs.
+> >> >=20
> >> > It *might* still work, since encoders set clock rate after TCON (at
> >> > least
> >> > that is my experience for HDMI pipeline), but that is still wrong.
-> >> >
+> >> >=20
> >> > To overcome above issue, I would stick to original proposal with
> >> > additional
> >> > clock specified in TCON TV DT node. That way TCON driver would always
@@ -299,79 +327,89 @@ napisal(a):
> >> > interfere
> >> > with setting clock rate, because TCON-TV0 clock would be decoupled in
> >> > TCON-TOP mux.
-> >> >
+> >> >=20
> >> > What do you think?
-> >>
+> >>=20
> >> I think this is the wrong representation, and worse, you are trying to
> >> work
> >> around software issues with it.
-> >>
-> >> So to confirm some details, the TVE expects 216 MHz clock, and it expects
+> >>=20
+> >> So to confirm some details, the TVE expects 216 MHz clock, and it expe=
+cts
> >> the TCON to run and output data at 216 MHz as well. Is that correct?
-> >
-> > Yes, from my understanding. 216 MHz is correct at least for PAL and NTSC,
+> >=20
+> > Yes, from my understanding. 216 MHz is correct at least for PAL and NTS=
+C,
> > e.g. TV mode. TVE on R40 is also capable of RGB mode (VGA connector).
-> >
-> >> Would any settings for the TCON differ between when HDMI or TVE is used?
-> >
+> >=20
+> >> Would any settings for the TCON differ between when HDMI or TVE is use=
+d?
+> >=20
> > Apart of clock, no, other settings would be the same.
-> >
+> >=20
> >> Does TVE and TCON run at 216 MHz regardless of resolution? I kind of
> >> doubt
> >> it. It might be expecting 297 MHz for PC resolutions.
-> >
+> >=20
> > Please check this table in BSP:
-> > https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/driver
+> > https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/dri=
+ver
> > s/ video/sunxi/disp2/tv/drv_tv.c#L24
-> >
+> >=20
> > 216 MHz is applicable for low resolution, interlaced modes. Modes like
> > 1080P, 1080I have expected standard timing.
->
+>=20
> That's weird. So it only applies to SDTV video resolutions. I remember
> seeing an "up sampling" setting for composite in the TVE, which goes all
> the way up to 216 MHz. Maybe that's the reason?
->
+>=20
-Probably. If upsampling is set to 0, it still needs 27 MHz, which is 2x more
-than standard PAL/NTSC clock. After studying AC200 manual (which is similar TV
-encoder) and its driver, it seems the reason for that is 8 bit parallel
+Probably. If upsampling is set to 0, it still needs 27 MHz, which is 2x mor=
+e=20
+than standard PAL/NTSC clock. After studying AC200 manual (which is similar=
+ TV=20
+encoder) and its driver, it seems the reason for that is 8 bit parallel=20
interface between TCON and TVE and 16 bit data (CCIR656).
However, actual tests would be needed to confirm all that.
> I wonder how the TCON manages this though. I mean with the dot clock this
> high, doesn't that mean the frame rate is much higher?
->
+>=20
-Not sure, but IMO it is downscaled somehow in TVE HW to get proper rates at
+Not sure, but IMO it is downscaled somehow in TVE HW to get proper rates at=
+=20
the end.
-> >> I think these kinds of quirks should be handled in the software, instead
+> >> I think these kinds of quirks should be handled in the software, inste=
+ad
> >> of
> >> being papered over.
-> >
+> >=20
> > Ok, that works for me too. I would just like to have such design that
> > would
> > later allow implementing TVE driver without much issues.
-> >
+> >=20
> > BTW, H3 TV TCON which is connected to TVE doesn't have TCON-TV channel
> > clock at all, since it is controlled with TVE clock (same case as it
> > would be here, if TCON TOP mux is switched to TVE clock source).
->
+>=20
> Does it require 216 MHz as well?
-Yes. It supports only PAL and NTSC (only one DAC), so BSP driver sets TVE
+Yes. It supports only PAL and NTSC (only one DAC), so BSP driver sets TVE=20
clock to 216 MHz.
->
+>=20
> > Maybe quirk can be added that it doesn't set clock rate at all if it is
> > connected to TVE?
->
+>=20
> A quirk yes. But the dot clock would be 216 MHz instead of not setting it,
-> and only for certain display modes. To be honest I think we can get by with
+> and only for certain display modes. To be honest I think we can get by wi=
+th
> just a TODO note for now.
-Why not leave control of channel rate to TVE, since it knows if oversampling
+Why not leave control of channel rate to TVE, since it knows if oversamplin=
+g=20
is enabled or not? But that's debate for another time.
I will send new R40 HDMI patches according your original proposal.
diff --git a/a/content_digest b/N2/content_digest
index 31ea73d..f0cc231 100644
--- a/a/content_digest
+++ b/N2/content_digest
@@ -42,60 +42,63 @@
]
[
"Dne ponedeljek, 25. junij 2018 ob 10:14:52 CEST je Chen-Yu Tsai napisal(a):\n",
- "> On Mon, Jun 25, 2018 at 3:58 PM, Jernej \305\240krabec\n",
- "> \n",
+ "> On Mon, Jun 25, 2018 at 3:58 PM, Jernej =C5=A0krabec\n",
+ ">=20\n",
"> <jernej.skrabec\@gmail.com> wrote:\n",
- "> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai \n",
+ "> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai=20\n",
"napisal(a):\n",
- "> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej \305\240krabec\n",
- "> >> \n",
+ "> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej =C5=A0krabec\n",
+ "> >>=20\n",
"> >> <jernej.skrabec\@gmail.com> wrote:\n",
- "> >> > Dne \304\215etrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej \305\240krabec \n",
+ "> >> > Dne =C4=8Detrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej =C5=A0kr=\n",
+ "abec=20\n",
"napisal(a):\n",
- "> >> >> Dne \304\215etrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai \n",
+ "> >> >> Dne =C4=8Detrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai=20\n",
"napisal(a):\n",
- "> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej \305\240krabec\n",
+ "> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej =C5=A0krabec\n",
"> >> >> > <jernej.skrabec\@siol.net>\n",
- "> >> >> \n",
+ "> >> >>=20\n",
"> >> >> wrote:\n",
"> >> >> > > Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai\n",
- "> > \n",
+ "> >=20\n",
"> > napisal(a):\n",
- "> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej \305\240krabec\n",
+ "> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej =C5=A0krabec\n",
"> >> >> > >> <jernej.skrabec\@siol.net>\n",
- "> >> >> > > \n",
+ "> >> >> > >=20\n",
"> >> >> > > wrote:\n",
"> >> >> > >> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > napisal(a):\n",
- "> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej \305\240krabec\n",
- "> >> >> > >> >> \n",
+ "> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej =C5=A0krabec\n",
+ "> >> >> > >> >>=20\n",
"> >> >> > >> >> <jernej.skrabec\@siol.net> wrote:\n",
"> >> >> > >> >> > Hi,\n",
- "> >> >> > >> >> > \n",
- "> >> >> > >> >> > Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripard\n",
- "> >> >> \n",
+ "> >> >> > >> >> >=20\n",
+ "> >> >> > >> >> > Dne petek, 15. junij 2018 ob 10:31:10 CEST je Maxime Ripa=\n",
+ "rd\n",
+ "> >> >>=20\n",
"> >> >> napisal(a):\n",
"> >> >> > >> >> >> Hi,\n",
- "> >> >> > >> >> >> \n",
+ "> >> >> > >> >> >>=20\n",
"> >> >> > >> >> >> On Tue, Jun 12, 2018 at 10:00:20PM +0200, Jernej Skrabec\n",
- "> > \n",
+ "> >=20\n",
"> > wrote:\n",
- "> >> >> > >> >> >> > TV TCONs connected to TCON TOP have to enable additional\n",
+ "> >> >> > >> >> >> > TV TCONs connected to TCON TOP have to enable addition=\n",
+ "al\n",
"> >> >> > >> >> >> > gate\n",
"> >> >> > >> >> >> > in\n",
"> >> >> > >> >> >> > order\n",
"> >> >> > >> >> >> > to work.\n",
- "> >> >> > >> >> >> > \n",
+ "> >> >> > >> >> >> >=20\n",
"> >> >> > >> >> >> > Add support for such TCONs.\n",
- "> >> >> > >> >> >> > \n",
+ "> >> >> > >> >> >> >=20\n",
"> >> >> > >> >> >> > Signed-off-by: Jernej Skrabec <jernej.skrabec\@siol.net>\n",
"> >> >> > >> >> >> > ---\n",
- "> >> >> > >> >> >> > \n",
+ "> >> >> > >> >> >> >=20\n",
"> >> >> > >> >> >> > drivers/gpu/drm/sun4i/sun4i_tcon.c | 11 +++++++++++\n",
"> >> >> > >> >> >> > drivers/gpu/drm/sun4i/sun4i_tcon.h | 4 ++++\n",
"> >> >> > >> >> >> > 2 files changed, 15 insertions(+)\n",
- "> >> >> > >> >> >> > \n",
+ "> >> >> > >> >> >> >=20\n",
"> >> >> > >> >> >> > diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c\n",
"> >> >> > >> >> >> > b/drivers/gpu/drm/sun4i/sun4i_tcon.c index\n",
"> >> >> > >> >> >> > 08747fc3ee71..0afb5a94a414\n",
@@ -106,16 +109,16 @@
"> >> >> > >> >> >> > sun4i_tcon_init_clocks(struct\n",
"> >> >> > >> >> >> > device\n",
"> >> >> > >> >> >> > *dev,\n",
- "> >> >> > >> >> >> > \n",
+ "> >> >> > >> >> >> >=20\n",
"> >> >> > >> >> >> > dev_err(dev, \"Couldn't get the TCON bus\n",
"> >> >> > >> >> >> > clock\\n\");\n",
"> >> >> > >> >> >> > return PTR_ERR(tcon->clk);\n",
- "> >> >> > >> >> >> > \n",
+ "> >> >> > >> >> >> > =20\n",
"> >> >> > >> >> >> > }\n",
- "> >> >> > >> >> >> > \n",
+ "> >> >> > >> >> >> >=20\n",
"> >> >> > >> >> >> > +\n",
"> >> >> > >> >> >> > + if (tcon->quirks->has_tcon_top_gate) {\n",
- "> >> >> > >> >> >> > + tcon->top_clk = devm_clk_get(dev,\n",
+ "> >> >> > >> >> >> > + tcon->top_clk =3D devm_clk_get(dev,\n",
"> >> >> > >> >> >> > \"tcon-top\");\n",
"> >> >> > >> >> >> > + if (IS_ERR(tcon->top_clk)) {\n",
"> >> >> > >> >> >> > + dev_err(dev, \"Couldn't get the TCON\n",
@@ -127,20 +130,23 @@
"> >> >> > >> >> >> > + clk_prepare_enable(tcon->top_clk);\n",
"> >> >> > >> >> >> > + }\n",
"> >> >> > >> >> >> > +\n",
- "> >> >> > >> >> >> \n",
- "> >> >> > >> >> >> Is it required for the TCON itself to operate, or does the\n",
+ "> >> >> > >> >> >>=20\n",
+ "> >> >> > >> >> >> Is it required for the TCON itself to operate, or does t=\n",
+ "he\n",
"> >> >> > >> >> >> TCON\n",
- "> >> >> > >> >> >> requires the TCON TOP, which in turn requires that clock to\n",
+ "> >> >> > >> >> >> requires the TCON TOP, which in turn requires that clock=\n",
+ " to\n",
"> >> >> > >> >> >> be\n",
"> >> >> > >> >> >> functional?\n",
- "> >> >> > >> >> >> \n",
- "> >> >> > >> >> >> I find it quite odd to have a clock that isn't meant for a\n",
+ "> >> >> > >> >> >>=20\n",
+ "> >> >> > >> >> >> I find it quite odd to have a clock that isn't meant for=\n",
+ " a\n",
"> >> >> > >> >> >> particular\n",
"> >> >> > >> >> >> device to actually be wired to another device. I'm not\n",
"> >> >> > >> >> >> saying\n",
"> >> >> > >> >> >> this\n",
"> >> >> > >> >> >> isn't the case, but it would be a first.\n",
- "> >> >> > >> >> > \n",
+ "> >> >> > >> >> >=20\n",
"> >> >> > >> >> > Documentation doesn't say much about that gate. I did few\n",
"> >> >> > >> >> > tests\n",
"> >> >> > >> >> > and\n",
@@ -149,23 +155,27 @@
"> >> >> > >> >> > gate\n",
"> >> >> > >> >> > is\n",
"> >> >> > >> >> > disabled. However, there is no image, as expected.\n",
- "> >> >> > >> >> \n",
+ "> >> >> > >> >>=20\n",
"> >> >> > >> >> The R40 manual does include it in the diagram, on page 504.\n",
"> >> >> > >> >> There's\n",
"> >> >> > >> >> also\n",
"> >> >> > >> >> a\n",
- "> >> >> > >> >> mux to select whether the clock comes directly from the CCU or\n",
+ "> >> >> > >> >> mux to select whether the clock comes directly from the CCU=\n",
+ " or\n",
"> >> >> > >> >> the\n",
"> >> >> > >> >> TV\n",
- "> >> >> > >> >> encoder (a feedback mode?). I assume this is the gate you are\n",
+ "> >> >> > >> >> encoder (a feedback mode?). I assume this is the gate you a=\n",
+ "re\n",
"> >> >> > >> >> referring\n",
"> >> >> > >> >> to\n",
- "> >> >> > >> >> here, in which case it is not a bus clock, but rather the TCON\n",
+ "> >> >> > >> >> here, in which case it is not a bus clock, but rather the T=\n",
+ "CON\n",
"> >> >> > >> >> module\n",
"> >> >> > >> >> or\n",
"> >> >> > >> >> channel clock, strangely routed.\n",
- "> >> >> > >> >> \n",
- "> >> >> > >> >> > More interestingly, I enabled test pattern directly in TCON\n",
+ "> >> >> > >> >>=20\n",
+ "> >> >> > >> >> > More interestingly, I enabled test pattern directly in TC=\n",
+ "ON\n",
"> >> >> > >> >> > to\n",
"> >> >> > >> >> > eliminate\n",
"> >> >> > >> >> > influence of the mixer. As soon as I disabled that gate,\n",
@@ -176,12 +186,15 @@
"> >> >> > >> >> > influences\n",
"> >> >> > >> >> > something\n",
"> >> >> > >> >> > inside TCON.\n",
- "> >> >> > >> >> > \n",
- "> >> >> > >> >> > Another test I did was that I moved enable/disable gate code\n",
+ "> >> >> > >> >> >=20\n",
+ "> >> >> > >> >> > Another test I did was that I moved enable/disable gate c=\n",
+ "ode\n",
"> >> >> > >> >> > to\n",
- "> >> >> > >> >> > sun4i_tcon_channel_set_status() and it worked just as well.\n",
- "> >> >> > >> >> > \n",
- "> >> >> > >> >> > I'll ask AW engineer what that gate actually does, but from\n",
+ "> >> >> > >> >> > sun4i_tcon_channel_set_status() and it worked just as wel=\n",
+ "l.\n",
+ "> >> >> > >> >> >=20\n",
+ "> >> >> > >> >> > I'll ask AW engineer what that gate actually does, but fr=\n",
+ "om\n",
"> >> >> > >> >> > what I\n",
"> >> >> > >> >> > saw,\n",
"> >> >> > >> >> > I\n",
@@ -199,12 +212,13 @@
"> >> >> > >> >> > doesn't\n",
"> >> >> > >> >> > sound\n",
"> >> >> > >> >> > right to me for some reason.\n",
- "> >> >> > >> >> \n",
+ "> >> >> > >> >>=20\n",
"> >> >> > >> >> If what I said above it true, then yes, the appropriate\n",
"> >> >> > >> >> location\n",
"> >> >> > >> >> to\n",
"> >> >> > >> >> enable\n",
- "> >> >> > >> >> it is the TCON driver, but moreover, the representation of the\n",
+ "> >> >> > >> >> it is the TCON driver, but moreover, the representation of =\n",
+ "the\n",
"> >> >> > >> >> clock\n",
"> >> >> > >> >> tree\n",
"> >> >> > >> >> should be fixed such that the TCON takes the clock from the\n",
@@ -216,124 +230,138 @@
"> >> >> > >> >> patch,\n",
"> >> >> > >> >> but\n",
"> >> >> > >> >> you'd add another for all the clock routing.\n",
- "> >> >> > >> > \n",
+ "> >> >> > >> >=20\n",
"> >> >> > >> > Can you be more specific? I not sure what you mean here.\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> For clock related properties in the device tree:\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> &tcon_top {\n",
- "> >> >> > >> \n",
- "> >> >> > >> clocks = <&ccu CLK_BUS_TCON_TOP>,\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
+ "> >> >> > >> clocks =3D <&ccu CLK_BUS_TCON_TOP>,\n",
+ "> >> >> > >> =20\n",
"> >> >> > >> <&ccu CLK_TCON_TV0>,\n",
"> >> >> > >> <&tve0>,\n",
"> >> >> > >> <&ccu CLK_TCON_TV1>,\n",
"> >> >> > >> <&tve1>;\n",
- "> >> >> > >> \n",
- "> >> >> > >> clock-names = \"bus\", \"tcon-tv0\", \"tve0\", \"tcon-tv1\", \"tve1\";\n",
- "> >> >> > >> clock-output-names = \"tcon-top-tv0\", \"tcon-top-tv1\";\n",
- "> >> >> > >> \n",
+ "> >> >> > >> =20\n",
+ "> >> >> > >> clock-names =3D \"bus\", \"tcon-tv0\", \"tve0\", \"tcon-tv1\", \"tv=\n",
+ "e1\";\n",
+ "> >> >> > >> clock-output-names =3D \"tcon-top-tv0\", \"tcon-top-tv1\";\n",
+ "> >> >> > >>=20\n",
"> >> >> > >> };\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> &tcon_tv0 {\n",
- "> >> >> > >> \n",
- "> >> >> > >> clocks = <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>'\n",
- "> >> >> > >> clock-names = \"ahb\", \"tcon-ch1\";\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
+ "> >> >> > >> clocks =3D <&ccu CLK_BUS_TCON_TV0>, <&tcon_top 0>'\n",
+ "> >> >> > >> clock-names =3D \"ahb\", \"tcon-ch1\";\n",
+ "> >> >> > >>=20\n",
"> >> >> > >> };\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> A diagram would look like:\n",
"> >> >> > >> | This part is TCON TOP |\n",
- "> >> >> > >> \n",
+ "> >> >> > >> =20\n",
"> >> >> > >> v v\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> CCU CLK_TCON_TV0 --|----\\ |\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> | mux ---- gate ----|-- TCON_TV0\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> TVE0 --------------|----/ |\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> And the same goes for TCON_TV1 and TVE1.\n",
- "> >> >> > >> \n",
+ "> >> >> > >>=20\n",
"> >> >> > >> The user manual is a bit lacking on how TVE outputs a clock\n",
"> >> >> > >> though.\n",
- "> >> >> > > \n",
- "> >> >> > > I didn't yet received any response on HW details from AW till now,\n",
+ "> >> >> > >=20\n",
+ "> >> >> > > I didn't yet received any response on HW details from AW till n=\n",
+ "ow,\n",
"> >> >> > > but I\n",
"> >> >> > > would like to post new version of patches soon.\n",
- "> >> >> > > \n",
+ "> >> >> > >=20\n",
"> >> >> > > While chaining like you described could be implemented easily, I\n",
"> >> >> > > don't\n",
"> >> >> > > think it really represents HW as it is. Tests showed that these\n",
"> >> >> > > two\n",
"> >> >> > > clocks are independent, otherwise register writes/reads wouldn't\n",
"> >> >> > > be\n",
- "> >> >> > > possible with tcon- top gate disabled. I chose tcon-top bus clock\n",
+ "> >> >> > > possible with tcon- top gate disabled. I chose tcon-top bus clo=\n",
+ "ck\n",
"> >> >> > > as\n",
"> >> >> > > a\n",
"> >> >> > > parent becase if it is not enabled, it simply won't work.\n",
- "> >> >> > \n",
- "> >> >> > AFAIK with the TCONs, even when the TCON channel clock (not the bus\n",
+ "> >> >> >=20\n",
+ "> >> >> > AFAIK with the TCONs, even when the TCON channel clock (not the b=\n",
+ "us\n",
"> >> >> > clock)\n",
"> >> >> > is disabled, register accesses still work.\n",
- "> >> >> \n",
+ "> >> >>=20\n",
"> >> >> You're right, I just tested that.\n",
- "> >> >> \n",
+ "> >> >>=20\n",
"> >> >> > I'm saying that the TCON TOP\n",
- "> >> >> > gate is downstream from the TCON channel clock in the CCU. These are\n",
+ "> >> >> > gate is downstream from the TCON channel clock in the CCU. These =\n",
+ "are\n",
"> >> >> > not\n",
"> >> >> > related to the TCON bus clock in the CCU, which affects register\n",
"> >> >> > access.\n",
- "> >> >> > \n",
- "> >> >> > Did Allwinner provide any information regarding the hierarchy of the\n",
+ "> >> >> >=20\n",
+ "> >> >> > Did Allwinner provide any information regarding the hierarchy of =\n",
+ "the\n",
"> >> >> > clocks?\n",
- "> >> >> \n",
+ "> >> >>=20\n",
"> >> >> No reponse for now.\n",
- "> >> >> \n",
+ "> >> >>=20\n",
"> >> >> > > However, if everyone feels chaining is the best way to implement\n",
"> >> >> > > it,\n",
"> >> >> > > I'll\n",
"> >> >> > > do it.\n",
- "> >> >> > \n",
- "> >> >> > I would like to get it right and match actual hardware. My proposal\n",
+ "> >> >> >=20\n",
+ "> >> >> > I would like to get it right and match actual hardware. My propos=\n",
+ "al\n",
"> >> >> > is\n",
"> >> >> > based on my understanding from the diagrams in the user manual.\n",
- "> >> >> \n",
+ "> >> >>=20\n",
"> >> >> So for now, your explanation is the most reasonable. Should we go\n",
"> >> >> ahead\n",
"> >> >> and\n",
"> >> >> implement your idea?\n",
- "> >> >> \n",
- "> >> >> Please note that H6 has TCON-TOP too, but it has only one LCD TCON and\n",
+ "> >> >>=20\n",
+ "> >> >> Please note that H6 has TCON-TOP too, but it has only one LCD TCON =\n",
+ "and\n",
"> >> >> one\n",
"> >> >> TV TCON instead of two of each kind. That means we will have hole in\n",
- "> >> >> indices (tcon_lcd0 is 1, tcon_tv0 is 3, which is aligned with R40) and\n",
- "> >> >> different TCON- TOP binding (no tcon_tv1 channel clock), but setup is\n",
+ "> >> >> indices (tcon_lcd0 is 1, tcon_tv0 is 3, which is aligned with R40) =\n",
+ "and\n",
+ "> >> >> different TCON- TOP binding (no tcon_tv1 channel clock), but setup =\n",
+ "is\n",
"> >> >> exactly the same.\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > I just noticed issue with this proposal. If we have following clock\n",
"> >> > chain\n",
"> >> > for HDMI, everythings is ok:\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > TCON-TV0 -> TCON-TOP-TV0\n",
- "> >> > \n",
- "> >> > TCON TV sets TCON-TOP-TV0 clock rate, which in turn sets TCON-TV0 clock\n",
+ "> >> >=20\n",
+ "> >> > TCON TV sets TCON-TOP-TV0 clock rate, which in turn sets TCON-TV0 cl=\n",
+ "ock\n",
"> >> > and\n",
"> >> > everything works.\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > However, when TVE will be configured, it would look like this:\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > TVE0 -> TCON-TOP-TV0\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > TVE driver will set TVE0 clock to 216 MHz and TCON TV would set\n",
- "> >> > TCON-TOP-TV0 rate which in turn sets TVE0 clock to something like 13.5\n",
- "> >> > MHz (or whatever is the right clock rate for PAL and NTSC). As you can\n",
- "> >> > see, same clock is set to two different rates by two different drivers.\n",
- "> >> > \n",
+ "> >> > TCON-TOP-TV0 rate which in turn sets TVE0 clock to something like 13=\n",
+ "=2E5\n",
+ "> >> > MHz (or whatever is the right clock rate for PAL and NTSC). As you c=\n",
+ "an\n",
+ "> >> > see, same clock is set to two different rates by two different drive=\n",
+ "rs.\n",
+ "> >> >=20\n",
"> >> > It *might* still work, since encoders set clock rate after TCON (at\n",
"> >> > least\n",
"> >> > that is my experience for HDMI pipeline), but that is still wrong.\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > To overcome above issue, I would stick to original proposal with\n",
"> >> > additional\n",
"> >> > clock specified in TCON TV DT node. That way TCON driver would always\n",
@@ -342,79 +370,89 @@
"> >> > interfere\n",
"> >> > with setting clock rate, because TCON-TV0 clock would be decoupled in\n",
"> >> > TCON-TOP mux.\n",
- "> >> > \n",
+ "> >> >=20\n",
"> >> > What do you think?\n",
- "> >> \n",
+ "> >>=20\n",
"> >> I think this is the wrong representation, and worse, you are trying to\n",
"> >> work\n",
"> >> around software issues with it.\n",
- "> >> \n",
- "> >> So to confirm some details, the TVE expects 216 MHz clock, and it expects\n",
+ "> >>=20\n",
+ "> >> So to confirm some details, the TVE expects 216 MHz clock, and it expe=\n",
+ "cts\n",
"> >> the TCON to run and output data at 216 MHz as well. Is that correct?\n",
- "> > \n",
- "> > Yes, from my understanding. 216 MHz is correct at least for PAL and NTSC,\n",
+ "> >=20\n",
+ "> > Yes, from my understanding. 216 MHz is correct at least for PAL and NTS=\n",
+ "C,\n",
"> > e.g. TV mode. TVE on R40 is also capable of RGB mode (VGA connector).\n",
- "> > \n",
- "> >> Would any settings for the TCON differ between when HDMI or TVE is used?\n",
- "> > \n",
+ "> >=20\n",
+ "> >> Would any settings for the TCON differ between when HDMI or TVE is use=\n",
+ "d?\n",
+ "> >=20\n",
"> > Apart of clock, no, other settings would be the same.\n",
- "> > \n",
+ "> >=20\n",
"> >> Does TVE and TCON run at 216 MHz regardless of resolution? I kind of\n",
"> >> doubt\n",
"> >> it. It might be expecting 297 MHz for PC resolutions.\n",
- "> > \n",
+ "> >=20\n",
"> > Please check this table in BSP:\n",
- "> > https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/driver\n",
+ "> > https://github.com/BPI-SINOVOIP/BPI-M2U-bsp/blob/master/linux-sunxi/dri=\n",
+ "ver\n",
"> > s/ video/sunxi/disp2/tv/drv_tv.c#L24\n",
- "> > \n",
+ "> >=20\n",
"> > 216 MHz is applicable for low resolution, interlaced modes. Modes like\n",
"> > 1080P, 1080I have expected standard timing.\n",
- "> \n",
+ ">=20\n",
"> That's weird. So it only applies to SDTV video resolutions. I remember\n",
"> seeing an \"up sampling\" setting for composite in the TVE, which goes all\n",
"> the way up to 216 MHz. Maybe that's the reason?\n",
- "> \n",
+ ">=20\n",
"\n",
- "Probably. If upsampling is set to 0, it still needs 27 MHz, which is 2x more \n",
- "than standard PAL/NTSC clock. After studying AC200 manual (which is similar TV \n",
- "encoder) and its driver, it seems the reason for that is 8 bit parallel \n",
+ "Probably. If upsampling is set to 0, it still needs 27 MHz, which is 2x mor=\n",
+ "e=20\n",
+ "than standard PAL/NTSC clock. After studying AC200 manual (which is similar=\n",
+ " TV=20\n",
+ "encoder) and its driver, it seems the reason for that is 8 bit parallel=20\n",
"interface between TCON and TVE and 16 bit data (CCIR656).\n",
"\n",
"However, actual tests would be needed to confirm all that.\n",
"\n",
"> I wonder how the TCON manages this though. I mean with the dot clock this\n",
"> high, doesn't that mean the frame rate is much higher?\n",
- "> \n",
+ ">=20\n",
"\n",
- "Not sure, but IMO it is downscaled somehow in TVE HW to get proper rates at \n",
+ "Not sure, but IMO it is downscaled somehow in TVE HW to get proper rates at=\n",
+ "=20\n",
"the end.\n",
"\n",
- "> >> I think these kinds of quirks should be handled in the software, instead\n",
+ "> >> I think these kinds of quirks should be handled in the software, inste=\n",
+ "ad\n",
"> >> of\n",
"> >> being papered over.\n",
- "> > \n",
+ "> >=20\n",
"> > Ok, that works for me too. I would just like to have such design that\n",
"> > would\n",
"> > later allow implementing TVE driver without much issues.\n",
- "> > \n",
+ "> >=20\n",
"> > BTW, H3 TV TCON which is connected to TVE doesn't have TCON-TV channel\n",
"> > clock at all, since it is controlled with TVE clock (same case as it\n",
"> > would be here, if TCON TOP mux is switched to TVE clock source).\n",
- "> \n",
+ ">=20\n",
"> Does it require 216 MHz as well?\n",
"\n",
- "Yes. It supports only PAL and NTSC (only one DAC), so BSP driver sets TVE \n",
+ "Yes. It supports only PAL and NTSC (only one DAC), so BSP driver sets TVE=20\n",
"clock to 216 MHz.\n",
"\n",
- "> \n",
+ ">=20\n",
"> > Maybe quirk can be added that it doesn't set clock rate at all if it is\n",
"> > connected to TVE?\n",
- "> \n",
+ ">=20\n",
"> A quirk yes. But the dot clock would be 216 MHz instead of not setting it,\n",
- "> and only for certain display modes. To be honest I think we can get by with\n",
+ "> and only for certain display modes. To be honest I think we can get by wi=\n",
+ "th\n",
"> just a TODO note for now.\n",
"\n",
- "Why not leave control of channel rate to TVE, since it knows if oversampling \n",
+ "Why not leave control of channel rate to TVE, since it knows if oversamplin=\n",
+ "g=20\n",
"is enabled or not? But that's debate for another time.\n",
"\n",
"I will send new R40 HDMI patches according your original proposal.\n",
@@ -423,4 +461,4 @@
"Jernej"
]
-ab4963801d28bf994b601f8eab77da38ebc56ea36ea55f1d48afd9251b618839
+dd445d665e5896717c008b509c3120f286a5cea676296e80ef4ca2c5a7162242
diff --git a/a/1.txt b/N3/1.txt
index 50fc6e9..e13ed4d 100644
--- a/a/1.txt
+++ b/N3/1.txt
@@ -1,31 +1,31 @@
Dne ponedeljek, 25. junij 2018 ob 10:14:52 CEST je Chen-Yu Tsai napisal(a):
-> On Mon, Jun 25, 2018 at 3:58 PM, Jernej Škrabec
+> On Mon, Jun 25, 2018 at 3:58 PM, Jernej ?krabec
>
> <jernej.skrabec@gmail.com> wrote:
> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai
napisal(a):
-> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej Škrabec
+> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej ?krabec
> >>
> >> <jernej.skrabec@gmail.com> wrote:
-> >> > Dne četrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej Škrabec
+> >> > Dne ?etrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej ?krabec
napisal(a):
-> >> >> Dne četrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai
+> >> >> Dne ?etrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai
napisal(a):
-> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej Škrabec
+> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej ?krabec
> >> >> > <jernej.skrabec@siol.net>
> >> >>
> >> >> wrote:
> >> >> > > Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai
> >
> > napisal(a):
-> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej Škrabec
+> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej ?krabec
> >> >> > >> <jernej.skrabec@siol.net>
> >> >> > >
> >> >> > > wrote:
> >> >> > >> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai
> >> >
> >> > napisal(a):
-> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej Škrabec
+> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej ?krabec
> >> >> > >> >>
> >> >> > >> >> <jernej.skrabec@siol.net> wrote:
> >> >> > >> >> > Hi,
diff --git a/a/content_digest b/N3/content_digest
index 31ea73d..8e77bbc 100644
--- a/a/content_digest
+++ b/N3/content_digest
@@ -8,31 +8,16 @@
"ref\0CAGb2v676mFiOry5eQabzkyVaQ6R64gT2_XuBzTAtHorNzfwCuw\@mail.gmail.com\0"
]
[
- "From\0Jernej \305\240krabec <jernej.skrabec\@gmail.com>\0"
+ "From\0jernej.skrabec\@gmail.com (Jernej \305\240krabec)\0"
]
[
- "Subject\0Re: [linux-sunxi] Re: [PATCH v2 11/27] drm/sun4i: tcon: Add support for tcon-top gate\0"
+ "Subject\0[linux-sunxi] Re: [PATCH v2 11/27] drm/sun4i: tcon: Add support for tcon-top gate\0"
]
[
"Date\0Mon, 25 Jun 2018 11:10:30 +0200\0"
]
[
- "To\0linux-sunxi\@googlegroups.com",
- " wens\@csie.org\0"
-]
-[
- "Cc\0Maxime Ripard <maxime.ripard\@bootlin.com>",
- " Rob Herring <robh+dt\@kernel.org>",
- " David Airlie <airlied\@linux.ie>",
- " Gustavo Padovan <gustavo\@padovan.org>",
- " Maarten Lankhorst <maarten.lankhorst\@linux.intel.com>",
- " Sean Paul <seanpaul\@chromium.org>",
- " Mark Rutland <mark.rutland\@arm.com>",
- " dri-devel <dri-devel\@lists.freedesktop.org>",
- " devicetree <devicetree\@vger.kernel.org>",
- " linux-arm-kernel <linux-arm-kernel\@lists.infradead.org>",
- " linux-kernel <linux-kernel\@vger.kernel.org>",
- " linux-clk <linux-clk\@vger.kernel.org>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -42,33 +27,33 @@
]
[
"Dne ponedeljek, 25. junij 2018 ob 10:14:52 CEST je Chen-Yu Tsai napisal(a):\n",
- "> On Mon, Jun 25, 2018 at 3:58 PM, Jernej \305\240krabec\n",
+ "> On Mon, Jun 25, 2018 at 3:58 PM, Jernej ?krabec\n",
"> \n",
"> <jernej.skrabec\@gmail.com> wrote:\n",
"> > Dne ponedeljek, 25. junij 2018 ob 05:51:41 CEST je Chen-Yu Tsai \n",
"napisal(a):\n",
- "> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej \305\240krabec\n",
+ "> >> On Mon, Jun 25, 2018 at 3:52 AM, Jernej ?krabec\n",
"> >> \n",
"> >> <jernej.skrabec\@gmail.com> wrote:\n",
- "> >> > Dne \304\215etrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej \305\240krabec \n",
+ "> >> > Dne ?etrtek, 21. junij 2018 ob 17:35:45 CEST je Jernej ?krabec \n",
"napisal(a):\n",
- "> >> >> Dne \304\215etrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai \n",
+ "> >> >> Dne ?etrtek, 21. junij 2018 ob 03:23:27 CEST je Chen-Yu Tsai \n",
"napisal(a):\n",
- "> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej \305\240krabec\n",
+ "> >> >> > On Thu, Jun 21, 2018 at 3:37 AM, Jernej ?krabec\n",
"> >> >> > <jernej.skrabec\@siol.net>\n",
"> >> >> \n",
"> >> >> wrote:\n",
"> >> >> > > Dne sobota, 16. junij 2018 ob 07:48:38 CEST je Chen-Yu Tsai\n",
"> > \n",
"> > napisal(a):\n",
- "> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej \305\240krabec\n",
+ "> >> >> > >> On Sat, Jun 16, 2018 at 1:33 AM, Jernej ?krabec\n",
"> >> >> > >> <jernej.skrabec\@siol.net>\n",
"> >> >> > > \n",
"> >> >> > > wrote:\n",
"> >> >> > >> > Dne petek, 15. junij 2018 ob 19:13:17 CEST je Chen-Yu Tsai\n",
"> >> > \n",
"> >> > napisal(a):\n",
- "> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej \305\240krabec\n",
+ "> >> >> > >> >> On Sat, Jun 16, 2018 at 12:41 AM, Jernej ?krabec\n",
"> >> >> > >> >> \n",
"> >> >> > >> >> <jernej.skrabec\@siol.net> wrote:\n",
"> >> >> > >> >> > Hi,\n",
@@ -423,4 +408,4 @@
"Jernej"
]
-ab4963801d28bf994b601f8eab77da38ebc56ea36ea55f1d48afd9251b618839
+47871edd0edb7d151a9f9618fca0e3d882fdae993e12677a0e5a613b71bc7653
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