Re: [RFC v1 06/11] clk: qcom: Add display clock controller driver for SM8350

From: Konrad Dybcio <konrad.dybcio@somainline.org>
To: Robert Foss <robert.foss@linaro.org>
Cc: Andy Gross <agross@kernel.org>,
	Bjorn Andersson <bjorn.andersson@linaro.org>,
	Michael Turquette <mturquette@baylibre.com>,
	Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
	Jonathan Marek <jonathan@marek.ca>,
	Taniya Das <tdas@codeaurora.org>,
	MSM <linux-arm-msm@vger.kernel.org>,
	"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
	"open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
	<devicetree@vger.kernel.org>,
	linux-kernel <linux-kernel@vger.kernel.org>,
	Vinod Koul <vinod.koul@linaro.org>
Subject: Re: [RFC v1 06/11] clk: qcom: Add display clock controller driver for SM8350
Date: Thu, 17 Jun 2021 21:37:12 +0200	[thread overview]
Message-ID: <243ab835-bc91-6cc6-a9ce-7be6763dc89e@somainline.org> (raw)
In-Reply-To: <CAG3jFysRuF=xkTaPK3efDW20cQ3hXLqqsT7J5YVgYvO1dmFOvA@mail.gmail.com>

>>> +
>>> +static struct pll_vco vco_table[] = {
>>> +     { 249600000, 1750000000, 0 },
>>> +};
>>> +
>>> +static const struct alpha_pll_config disp_cc_pll0_config = {
>>> +     .l = 0x47,
>> Is the ".cal_l = 0x44," part from downstream not necessary?
> Yes it is. I went back and forth about  'cal_l', but in the end the
> only value it is ever set to is 0x44, which is also what the default
> value is. So there is no need for representing it explicitly at the
> moment.

Interesting, maybe it'll be required for next SoCs..

>>> +};
>>> +
>>> +static const struct alpha_pll_config disp_cc_pll1_config = {
>>> +     .l = 0x1F,
>> Ditto
> Sorry, ditto what?

Aah, sorry I cut out a ".cal_l  = 0x44" line while adding my comments..

Konrad