[U-Boot] [PULL] u-boot-socfpga/master

From: Marek Vasut <marex@denx.de>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PULL] u-boot-socfpga/master
Date: Sun, 12 May 2019 01:56:20 +0200	[thread overview]
Message-ID: <32a68f0c-aedd-67e7-ff60-c4472d6e906e@denx.de> (raw)

A10 FPGA programming support, Gen5 livetree conversion

The following changes since commit 82da478b8f8ed41ed8bdbd0269da36ef6aaef7e8:

  Merge branch '2019-05-10-master-imports' (2019-05-10 11:08:48 -0400)

are available in the Git repository at:

  git://git.denx.de/u-boot-socfpga.git master

for you to fetch changes up to 1b898ffc040b5977a07af755b8ba3aa151914800:

  gpio: dwapb_gpio: convert to livetree (2019-05-10 22:48:11 +0200)

----------------------------------------------------------------
Ley Foon Tan (1):
      configs: stratix10: Enable CONFIG_SPI_FLASH_USE_4K_SECTORS

Simon Goldschmidt (6):
      timer: dw-apb: remove unused DECLARE_GLOBAL_DATA_PTR
      spi: cadence_qspi: convert to livetree
      spi: designware: convert to livetree
      serial: altera_uart: convert to livetree
      reset: socfpga: convert to livetree
      gpio: dwapb_gpio: convert to livetree

Tien Fong Chee (9):
      ARM: socfpga: Description on FPGA bitstream type and file name for
Arria 10
      ARM: socfpga: Add default FPGA bitstream fitImage for Arria10 SoCDK
      ARM: socfpga: Cleaning up and ensuring consistent format messages
in driver
      ARM: socfpga: Moving the watchdog reset to the for-loop status polling
      ARM: socfpga: Add FPGA drivers for Arria 10 FPGA bitstream loading
      ARM: socfpga: Add the configuration for FPGA SoCFPGA A10 SoCDK
      spl: socfpga: Implement fpga bitstream loading with socfpga loadfs
      ARM: socfpga: Synchronize the configuration for A10 SoCDK
      ARM: socfpga: Increase Malloc pool size to support FAT filesystem
in SPL

 arch/arm/dts/socfpga_arria10_socdk_sdmmc.dts                  |  17 +++++
 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h     |  40
+++++++++-
 arch/arm/mach-socfpga/spl_a10.c                               |  31
+++++++-
 board/altera/arria10-socdk/fit_spl_fpga.its                   |  38
++++++++++
 configs/socfpga_arria10_defconfig                             |  23 +++++-
 configs/socfpga_stratix10_defconfig                           |   1 -
 doc/device-tree-bindings/fpga/altera-socfpga-a10-fpga-mgr.txt |  26 ++++++-
 drivers/fpga/socfpga_arria10.c                                | 514
+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++------
 drivers/gpio/dwapb_gpio.c                                     |  25 +++----
 drivers/reset/reset-socfpga.c                                 |   4 +-
 drivers/serial/altera_uart.c                                  |   5 +-
 drivers/spi/cadence_qspi.c                                    |  39
+++++-----
 drivers/spi/designware_spi.c                                  |   8 +-
 drivers/timer/dw-apb-timer.c                                  |   2 -
 include/configs/socfpga_arria10_socdk.h                       |   5 +-
 include/image.h                                               |   4 +
 16 files changed, 702 insertions(+), 80 deletions(-)
 create mode 100644 board/altera/arria10-socdk/fit_spl_fpga.its