From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:56592) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UxGGO-0008Kd-Uj for qemu-devel@nongnu.org; Thu, 11 Jul 2013 08:46:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1UxGGN-0006Yl-9L for qemu-devel@nongnu.org; Thu, 11 Jul 2013 08:46:24 -0400 Received: from cantor2.suse.de ([195.135.220.15]:43720 helo=mx2.suse.de) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1UxGGM-0006Ya-V4 for qemu-devel@nongnu.org; Thu, 11 Jul 2013 08:46:23 -0400 Message-ID: <51DEA91B.40903@suse.de> Date: Thu, 11 Jul 2013 14:46:19 +0200 From: =?ISO-8859-1?Q?Andreas_F=E4rber?= MIME-Version: 1.0 References: <51C75FA6.6080903@reactos.org> <51C7E21A.9090005@web.de> <8A36D64D-0625-49E1-9E59-391DAEEBD1FC@suse.de> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: quoted-printable Subject: Re: [Qemu-devel] [PATCH v3 11/14] ioport: Switch dispatching to memory core layer List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: Paolo Bonzini , Liu Ping Fan , Jan Kiszka , qemu-devel , =?ISO-8859-1?Q?Herv=E9_Poussineau?= Am 11.07.2013 14:34, schrieb Alexander Graf: >=20 > On 11.07.2013, at 14:29, Alexander Graf wrote: >=20 >> >> On 24.06.2013, at 08:07, Jan Kiszka wrote: >> >>> On 2013-06-23 22:50, Herv=E9 Poussineau wrote: >>>> Jan Kiszka a =E9crit : >>>>> From: Jan Kiszka >>>>> >>>>> The current ioport dispatcher is a complex beast, mostly due to the >>>>> need to deal with old portio interface users. But we can overcome i= t >>>>> without converting all portio users by embedding the required base >>>>> address of a MemoryRegionPortio access into that data structure. Th= at >>>>> removes the need to have the additional MemoryRegionIORange structu= re >>>>> in the loop on every access. >>>>> >>>>> To handle old portio memory ops, we simply install dispatching hand= lers >>>>> for portio memory regions when registering them with the memory cor= e. >>>>> This removes the need for the old_portio field. >>>>> >>>>> We can drop the additional aliasing of ioport regions and also the >>>>> special address space listener. cpu_in and cpu_out now simply call >>>>> address_space_read/write. And we can concentrate portio handling in= a >>>>> single source file. >>>>> >>>>> Signed-off-by: Jan Kiszka >>>>> --- >>>> >>>> ... >>>> >>>>> + >>>>> +static void portio_write(void *opaque, hwaddr addr, uint64_t data, >>>>> + unsigned size) >>>>> +{ >>>>> + MemoryRegionPortioList *mrpio =3D opaque; >>>>> + const MemoryRegionPortio *mrp =3D find_portio(mrpio, addr, siz= e, >>>>> true); >>>>> + >>>>> + if (mrp) { >>>>> + mrp->write(mrpio->portio_opaque, mrp->base + addr, data); >>>>> + } else if (size =3D=3D 2) { >>>>> + mrp =3D find_portio(mrpio, addr, 1, true); >>>>> + assert(mrp); >>>>> + mrp->write(mrpio->portio_opaque, mrp->base + addr, data & = 0xff); >>>>> + mrp->write(mrpio->portio_opaque, mrp->base + addr + 1, dat= a >>>>>>> 8); >>>>> + } >>>>> +} >>>>> + >>>>> +static const MemoryRegionOps portio_ops =3D { >>>>> + .read =3D portio_read, >>>>> + .write =3D portio_write, >>>>> + .valid.unaligned =3D true, >>>>> + .impl.unaligned =3D true, >>>>> +}; >>>>> + >>>> >>>> You need to mark these operations as DEVICE_LITTLE_ENDIAN. >>>> In portio_write above, you clearly assume that data is in LE format. >>> >>> Anything behind PIO is little endian, of course. Will add this. >> >> This patch breaks VGA on PPC as it is in master today. >=20 > If I don't mark portio as little endian it works as expected. There's p= robably someone swapping things twice. sPAPR has its MemoryRegion marked Little Endian: http://git.qemu.org/?p=3Dqemu.git;a=3Dblobdiff;f=3Dhw/spapr_pci.c;h=3Da08= ed11166595bdc493065beb64d4ce5b7b0dded;hp=3Dc2c3079d21d5be2647faf85a8c608a= c995d2ca62;hb=3Da3cfa18eb075c7ef78358ca1956fe7b01caa1724;hpb=3D286d52ebfc= 0d0d53c2a878e454292fea14bad41b Possibly we can now apply Herv=E9's patches on top to remove that hack ag= ain? Andreas --=20 SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 N=FCrnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imend=F6rffer; HRB 16746 AG N=FCrnbe= rg