From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:36704) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YseFu-0006tV-Lp for qemu-devel@nongnu.org; Wed, 13 May 2015 17:31:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YseFq-0000nX-MM for qemu-devel@nongnu.org; Wed, 13 May 2015 17:31:54 -0400 Received: from mail-qk0-x22b.google.com ([2607:f8b0:400d:c09::22b]:35341) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YseFq-0000nS-Gf for qemu-devel@nongnu.org; Wed, 13 May 2015 17:31:50 -0400 Received: by qkgy4 with SMTP id y4so37822819qkg.2 for ; Wed, 13 May 2015 14:31:50 -0700 (PDT) Sender: Richard Henderson Message-ID: <5553C2C2.2020601@twiddle.net> Date: Wed, 13 May 2015 14:31:46 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1431531457-17127-1-git-send-email-yongbok.kim@imgtec.com> <1431531457-17127-3-git-send-email-yongbok.kim@imgtec.com> <5553A5C4.6030902@twiddle.net> <5553ACF2.7050708@twiddle.net> <5553BB40.7050706@imgtec.com> In-Reply-To: <5553BB40.7050706@imgtec.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Leon Alrae Cc: Yongbok Kim , peter.maydell@linaro.org, qemu-devel@nongnu.org, "Maciej W. Rozycki" , afaerber@suse.de On 05/13/2015 01:59 PM, Leon Alrae wrote: > On 13/05/15 20:58, Richard Henderson wrote: >> On 05/13/2015 12:56 PM, Maciej W. Rozycki wrote: >>> We must have a way to deal with memory access operations issued by a >>> single machine instruction crossing a page boundary already as this is >>> what MIPS16 SAVE and RESTORE instructions as well as microMIPS SWP, SDP, >>> SWM, SDM, LWP, LDP, LWM and LDM ones do. Perhaps these are worth >>> looking into and their approach copying (or reusing) here? >> >> Certainly we do. It's all in softmmu_template.h. > > I believe the problem is that MSA vector register's size is 16-bytes > (this DATA_SIZE isn't supported in softmmu_template) and MSA load/store > is supposed to be atomic. What I meant is that the code to handle page boundary crosses is there in softmmu_template.h. If you want to copy that mechanism into the mips backend, that's where you should start. r~