Re: [PATCH] x86, mce, amd: Read mcgstatus before we log the error

From: Aravind Gopalakrishnan <aravind.gopalakrishnan@amd.com>
To: Borislav Petkov <bp@alien8.de>
Cc: <tony.luck@intel.com>, <tglx@linutronix.de>, <mingo@redhat.com>,
	<hpa@zytor.com>, <x86@kernel.org>, <linux-edac@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] x86, mce, amd: Read mcgstatus before we log the error
Date: Thu, 14 May 2015 09:56:07 -0500	[thread overview]
Message-ID: <5554B787.4020400@amd.com> (raw)
In-Reply-To: <20150514095006.GB29125@pd.tnic>

On 5/14/2015 4:50 AM, Borislav Petkov wrote:
> On Wed, May 13, 2015 at 12:37:04PM -0500, Aravind Gopalakrishnan wrote:
>>   
>>   	mce_setup(&m);
>> +	rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus);
> Any meaningful bits in that MSR we wanna know when getting a
> thresholding or deferred error? Are they even defined?

Ah. Good point. RIPV is not defined for Deferred errors.
For thresholding, we'll hit the interrupt handler only if we hit the 
threshold and
it is not UC error (for which RIPV is not defined). Else, the counter 
would be incremented,
but it would cause a #MC anyway.

> If yes, RIPV should always be 1b, EIPV too, MCIP can't be set.
>
> -ENOMOREUSEFULBITS.
>

Thanks,
-Aravind.