From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55397) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ysy7y-0003uH-LX for qemu-devel@nongnu.org; Thu, 14 May 2015 14:45:03 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Ysy7u-0001gU-Io for qemu-devel@nongnu.org; Thu, 14 May 2015 14:45:02 -0400 Received: from mail-qg0-x22e.google.com ([2607:f8b0:400d:c04::22e]:34285) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Ysy7u-0001gI-E3 for qemu-devel@nongnu.org; Thu, 14 May 2015 14:44:58 -0400 Received: by qgfi89 with SMTP id i89so42130548qgf.1 for ; Thu, 14 May 2015 11:44:58 -0700 (PDT) Sender: Richard Henderson Message-ID: <5554ED26.3030403@twiddle.net> Date: Thu, 14 May 2015 11:44:54 -0700 From: Richard Henderson MIME-Version: 1.0 References: <1431531457-17127-1-git-send-email-yongbok.kim@imgtec.com> <1431531457-17127-3-git-send-email-yongbok.kim@imgtec.com> <5553A5C4.6030902@twiddle.net> <5554641F.30308@imgtec.com> <55546EFB.7060702@imgtec.com> In-Reply-To: <55546EFB.7060702@imgtec.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v3 2/2] target-mips: Misaligned memory accesses for MSA List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Yongbok Kim , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, leon.alrae@imgtec.com, afaerber@suse.de On 05/14/2015 02:46 AM, Yongbok Kim wrote: > In addition to that, if we issue all the loads let say only the first page is > accessible, in the architectural point of view it would be fine as nothing will > be stored in the vector register but accessing the first page is "visible" from > the data bus. > Do you think this wouldn't cause any problem? > It might be just implementation dependent though. I don't think it would cause a problem unless the user is silly enough to issue an MSA read to device memory. r~