From: "Jan Beulich" <JBeulich@suse.com>
To: xen-devel <xen-devel@lists.xenproject.org>
Cc: Ian Campbell <Ian.Campbell@eu.citrix.com>,
Keir Fraser <keir@xen.org>,
Ian Jackson <Ian.Jackson@eu.citrix.com>, Tim Deegan <tim@xen.org>
Subject: [PATCH 1/4] ns16550: store pointer to config parameters for PCI
Date: Tue, 23 Feb 2016 04:28:18 -0700 [thread overview]
Message-ID: <56CC506202000078000D52AD@prv-mh.provo.novell.com> (raw)
In-Reply-To: <56CC4F0B02000078000D5290@prv-mh.provo.novell.com>
[-- Attachment #1: Type: text/plain, Size: 4231 bytes --]
Subsequent changes will want to use this pointer.
This makes the enable_ro structure member redundant, so it gets dropped
at once.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -74,7 +74,7 @@ static struct ns16550 {
u32 bar64;
u16 cr;
u8 bar_idx;
- bool_t enable_ro; /* Make MMIO devices read only to Dom0 */
+ const struct ns16550_config_param *param; /* Points into .init.*! */
#endif
} ns16550_com[2] = { { 0 } };
@@ -624,7 +624,7 @@ static void __init ns16550_init_postirq(
#ifdef CONFIG_HAS_PCI
if ( uart->bar || uart->ps_bdf_enable )
{
- if ( !uart->enable_ro )
+ if ( !uart->param )
pci_hide_device(uart->ps_bdf[0], PCI_DEVFN(uart->ps_bdf[1],
uart->ps_bdf[2]));
else
@@ -900,7 +900,7 @@ pci_uart_config(struct ns16550 *uart, bo
/* Check for params in uart_config lookup table */
for ( i = 0; i < ARRAY_SIZE(uart_config); i++)
{
- unsigned int p;
+ const struct ns16550_config_param *param;
if ( uart_config[i].vendor_id != vendor )
continue;
@@ -908,33 +908,34 @@ pci_uart_config(struct ns16550 *uart, bo
if ( uart_config[i].dev_id != device )
continue;
- p = uart_config[i].param;
+ param = uart_param + uart_config[i].param;
+
/*
* Force length of mmio region to be at least
* 8 bytes times (1 << reg_shift)
*/
- if ( size < (0x8 * (1 << uart_param[p].reg_shift)) )
+ if ( size < (0x8 * (1 << param->reg_shift)) )
continue;
- if ( bar_idx >= uart_param[p].max_bars )
+ if ( bar_idx >= param->max_bars )
continue;
- if ( uart_param[p].fifo_size )
- uart->fifo_size = uart_param[p].fifo_size;
+ uart->param = param;
+
+ if ( param->fifo_size )
+ uart->fifo_size = param->fifo_size;
- uart->reg_shift = uart_param[p].reg_shift;
- uart->reg_width = uart_param[p].reg_width;
- uart->lsr_mask = uart_param[p].lsr_mask;
+ uart->reg_shift = param->reg_shift;
+ uart->reg_width = param->reg_width;
+ uart->lsr_mask = param->lsr_mask;
uart->io_base = ((u64)bar_64 << 32) |
(bar & PCI_BASE_ADDRESS_MEM_MASK);
- uart->io_base += uart_param[p].first_offset;
- uart->io_base += bar_idx * uart_param[p].uart_offset;
- if ( uart_param[p].base_baud )
- uart->clock_hz = uart_param[p].base_baud * 16;
- size = max(8U << uart_param[p].reg_shift,
- uart_param[p].uart_offset);
- /* Set device and MMIO region read only to Dom0 */
- uart->enable_ro = 1;
+ uart->io_base += param->first_offset;
+ uart->io_base += bar_idx * param->uart_offset;
+ if ( param->base_baud )
+ uart->clock_hz = param->base_baud * 16;
+ size = max(8U << param->reg_shift,
+ param->uart_offset);
break;
}
@@ -1094,10 +1095,6 @@ static void ns16550_init_common(struct n
{
uart->clock_hz = UART_CLOCK_HZ;
-#ifdef CONFIG_HAS_PCI
- uart->enable_ro = 0;
-#endif
-
/* Default is no transmit FIFO. */
uart->fifo_size = 1;
[-- Attachment #2: ns16550-replace-enable_ro.patch --]
[-- Type: text/plain, Size: 4282 bytes --]
ns16550: store pointer to config parameters for PCI
Subsequent changes will want to use this pointer.
This makes the enable_ro structure member redundant, so it gets dropped
at once.
Signed-off-by: Jan Beulich <jbeulich@suse.com>
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -74,7 +74,7 @@ static struct ns16550 {
u32 bar64;
u16 cr;
u8 bar_idx;
- bool_t enable_ro; /* Make MMIO devices read only to Dom0 */
+ const struct ns16550_config_param *param; /* Points into .init.*! */
#endif
} ns16550_com[2] = { { 0 } };
@@ -624,7 +624,7 @@ static void __init ns16550_init_postirq(
#ifdef CONFIG_HAS_PCI
if ( uart->bar || uart->ps_bdf_enable )
{
- if ( !uart->enable_ro )
+ if ( !uart->param )
pci_hide_device(uart->ps_bdf[0], PCI_DEVFN(uart->ps_bdf[1],
uart->ps_bdf[2]));
else
@@ -900,7 +900,7 @@ pci_uart_config(struct ns16550 *uart, bo
/* Check for params in uart_config lookup table */
for ( i = 0; i < ARRAY_SIZE(uart_config); i++)
{
- unsigned int p;
+ const struct ns16550_config_param *param;
if ( uart_config[i].vendor_id != vendor )
continue;
@@ -908,33 +908,34 @@ pci_uart_config(struct ns16550 *uart, bo
if ( uart_config[i].dev_id != device )
continue;
- p = uart_config[i].param;
+ param = uart_param + uart_config[i].param;
+
/*
* Force length of mmio region to be at least
* 8 bytes times (1 << reg_shift)
*/
- if ( size < (0x8 * (1 << uart_param[p].reg_shift)) )
+ if ( size < (0x8 * (1 << param->reg_shift)) )
continue;
- if ( bar_idx >= uart_param[p].max_bars )
+ if ( bar_idx >= param->max_bars )
continue;
- if ( uart_param[p].fifo_size )
- uart->fifo_size = uart_param[p].fifo_size;
+ uart->param = param;
+
+ if ( param->fifo_size )
+ uart->fifo_size = param->fifo_size;
- uart->reg_shift = uart_param[p].reg_shift;
- uart->reg_width = uart_param[p].reg_width;
- uart->lsr_mask = uart_param[p].lsr_mask;
+ uart->reg_shift = param->reg_shift;
+ uart->reg_width = param->reg_width;
+ uart->lsr_mask = param->lsr_mask;
uart->io_base = ((u64)bar_64 << 32) |
(bar & PCI_BASE_ADDRESS_MEM_MASK);
- uart->io_base += uart_param[p].first_offset;
- uart->io_base += bar_idx * uart_param[p].uart_offset;
- if ( uart_param[p].base_baud )
- uart->clock_hz = uart_param[p].base_baud * 16;
- size = max(8U << uart_param[p].reg_shift,
- uart_param[p].uart_offset);
- /* Set device and MMIO region read only to Dom0 */
- uart->enable_ro = 1;
+ uart->io_base += param->first_offset;
+ uart->io_base += bar_idx * param->uart_offset;
+ if ( param->base_baud )
+ uart->clock_hz = param->base_baud * 16;
+ size = max(8U << param->reg_shift,
+ param->uart_offset);
break;
}
@@ -1094,10 +1095,6 @@ static void ns16550_init_common(struct n
{
uart->clock_hz = UART_CLOCK_HZ;
-#ifdef CONFIG_HAS_PCI
- uart->enable_ro = 0;
-#endif
-
/* Default is no transmit FIFO. */
uart->fifo_size = 1;
[-- Attachment #3: Type: text/plain, Size: 126 bytes --]
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next prev parent reply other threads:[~2016-02-23 11:28 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-23 11:22 [PATCH 0/4] ns16550: enable support for Pericom controllers Jan Beulich
2016-02-23 11:28 ` Jan Beulich [this message]
2016-03-07 21:06 ` [PATCH 1/4] ns16550: store pointer to config parameters for PCI Konrad Rzeszutek Wilk
2016-02-23 11:28 ` [PATCH 2/4] ns16550: enable Pericom controller support Jan Beulich
2016-03-07 22:04 ` Konrad Rzeszutek Wilk
2016-03-08 8:48 ` Jan Beulich
2016-03-09 16:52 ` Konrad Rzeszutek Wilk
2016-03-09 17:01 ` Jan Beulich
2016-03-11 2:31 ` Konrad Rzeszutek Wilk
2016-03-11 11:02 ` Jan Beulich
2016-03-22 13:19 ` [PATCH v2 " Jan Beulich
2016-03-28 14:46 ` Konrad Rzeszutek Wilk
2016-02-23 11:30 ` [PATCH 3/4] console: adjust IRQ initialization Jan Beulich
2016-03-07 22:10 ` Konrad Rzeszutek Wilk
2016-02-23 11:30 ` [PATCH RFC 4/4] ns16550: enable use of PCI MSI Jan Beulich
2016-02-29 16:56 ` [PATCH 0/4] ns16550: enable support for Pericom controllers Konrad Rzeszutek Wilk
2016-02-29 17:03 ` Jan Beulich
2016-03-04 13:19 ` Ping: " Jan Beulich
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