From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752250AbcGACMI (ORCPT ); Thu, 30 Jun 2016 22:12:08 -0400 Received: from regular1.263xmail.com ([211.150.99.132]:50672 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751996AbcGACMF (ORCPT ); Thu, 30 Jun 2016 22:12:05 -0400 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 X-RL-SENDER: wxt@rock-chips.com X-FST-TO: heiko@sntech.de X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: wxt@rock-chips.com X-UNIQUE-TAG: <4b1b6d62e0b82a192737e9d4bad593ea> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Message-ID: <5775D14C.5040808@rock-chips.com> Date: Fri, 01 Jul 2016 10:11:24 +0800 From: Caesar Wang User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Heiko Stuebner , Doug Anderson CC: Xu Jianqun , Brian Norris , "linux-kernel@vger.kernel.org" , "open list:ARM/Rockchip SoC..." , "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , Elaine Zhang , huangtao Subject: Re: [PATCH] arm64: dts: rockchip: add the power domain node for rk3399 References: <1467251760-14695-1-git-send-email-wxt@rock-chips.com> <2709691.LCsUme3dJo@phil> In-Reply-To: <2709691.LCsUme3dJo@phil> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Thanks your reviewing! On 2016年07月01日 05:57, Heiko Stuebner wrote: > Am Donnerstag, 30. Juni 2016, 14:49:41 schrieb Doug Anderson: >> Caesar, >> >> On Wed, Jun 29, 2016 at 6:56 PM, Caesar Wang wrote: >>> From: Elaine Zhang >>> >>> In order to meet low power requirements, a power management unit (PMU) >>> is >>> designed for controlling power resources in RK3399. The RK3399 PMU is >>> dedicated for managing the power of the whole chip. >>> >>> 1. add pd node for RK3399 Soc >>> 2. create power domain tree >>> 3. add qos node for domain >>> >>> From the DT/binds and driver can get more detail information: >>> The driver: >>> drivers/soc/rockchip/pm_domains.c >>> The document: >>> Documentation/devicetree/bindings/soc/rockchip/power_domain.txt >>> >>> --- >>> >>> Tested on vop and gpu devices added for next kernel. >>> PD: >>> localhost / # cat sys/kernel/debug/pm_genpd/pm_genpd_summary >> Nit: can you put a "/" before "sys" here and elsewhere in your patches? >> >>> domain status slaves >>> /device runtime status >>> ---------------------------------------------------------------------- >>> pd_gpu on >>> /devices/platform/ff9a0000.gpu active >>> pd_vopl off >>> /devices/platform/ff8f0000.vop suspended >>> pd_vopb off >>> /devices/platform/ff900000.vop suspended >>> pd_vo off pd_vopb, pd_vopl >>> pd_hdcp off >>> ... >>> pd_iep off >>> pd_vcodec off >>> pd_vdu off >>> >>> QOS: >>> localhost / # cat sys/kernel/debug/pm_qos/ >>> cpu_dma_latency network_latency >>> memory_bandwidth network_throughput >> What is this supposed to be showing exactly? You can't "cat" a >> directory, so maybe you meant "ls"? >> >> Also, each of these files contains the string "Empty!" and these files >> seem fairly unconnected to your patch. Those files exist both before >> and after your patch and nothing that I can see in the Rockchip QoS >> stuff hooks up to the generic Linux QoS infrastructure. The power >> domains just save and restore the QoS--they don't actually allow >> settting it. > personally, I would just drop that debugfs-dump, as I don't see what we gain > from it :-). Agreed, drop it. >>> Signed-off-by: Elaine Zhang >>> Signed-off-by: Caesar Wang >>> --- > [...] > >>> + pmu: power-management@ff310000 { >>> + compatible = "rockchip,rk3399-pmu", "syscon", >>> "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; >>> + >>> + power: power-controller { >>> + status = "okay"; >>> + compatible = "rockchip,rk3399-power-controller"; >>> + #power-domain-cells = <1>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + pd_vdu { >>> + reg = ; >>> + clocks = <&cru ACLK_VDU>, >>> + <&cru HCLK_VDU>; >>> + pm_qos = <&qos_video_m1_r>, >>> + <&qos_video_m1_w>; >>> + }; >>> + pd_vcodec { >>> + reg = ; >>> + clocks = <&cru ACLK_VCODEC>, >>> + <&cru HCLK_VCODEC>; >>> + pm_qos = <&qos_video_m0>; >>> + }; >>> + pd_iep { >>> + reg = ; >>> + clocks = <&cru ACLK_IEP>, >>> + <&cru HCLK_IEP>; >>> + pm_qos = <&qos_iep>; >>> + }; >>> + pd_rga { >>> + reg = ; >>> + clocks = <&cru ACLK_RGA>, >>> + <&cru HCLK_RGA>; >>> + pm_qos = <&qos_rga_r>, >>> + <&qos_rga_w>; >>> + }; >>> + pd_vio { >>> + reg = ; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + pd_isp0 { >>> + reg = ; >>> + clocks = <&cru ACLK_ISP0>, >>> + <&cru HCLK_ISP0>; >>> + pm_qos = <&qos_isp0_m0>, >>> + <&qos_isp0_m1>; >>> + }; >>> + pd_isp1 { >>> + reg = ; >>> + clocks = <&cru ACLK_ISP1>, >>> + <&cru HCLK_ISP1>; >>> + pm_qos = <&qos_isp1_m0>, >>> + <&qos_isp1_m1>; >>> + }; >>> + pd_hdcp { >>> + reg = ; >>> + clocks = <&cru ACLK_HDCP>, >>> + <&cru HCLK_HDCP>, >>> + <&cru PCLK_HDCP>; >>> + pm_qos = <&qos_hdcp>; >>> + }; >>> + pd_vo { >>> + reg = ; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + pd_vopb { >>> + reg = ; >>> + clocks = <&cru >>> ACLK_VOP0>, + >>> <&cru HCLK_VOP0>; + >>> pm_qos = <&qos_vop_big_r>, + >>> <&qos_vop_big_w>; + >>> }; >>> + pd_vopl { >>> + reg = ; >>> + clocks = <&cru >>> ACLK_VOP1>, + >>> <&cru HCLK_VOP1>; + >>> pm_qos = <&qos_vop_little>; + }; >>> + }; >>> + }; >>> + pd_gpu { >>> + reg = ; >>> + clocks = <&cru ACLK_GPU>; >>> + pm_qos = <&qos_gpu>; >>> + }; >> Again a nitty sort order question. Is there a reason not to make >> things alphabetical? AKA: pd_gpu, pd_iep, pd_rga, ... >> >> ...and inside pd_vio should be alphabetical too? >> >> In the TRM it looks like some of the power domains are grouped >> together (like all the domains under LOGIC or CENTERLOGIC). If >> keeping that grouping makes sense here then you should add a comment >> at the start of each group and sort the groups sanely (and sort within >> each group). Okay, let me see it. Thanks! >> >> It looks like there are also more power domains that you haven't >> listed here (like PD_GMAC, for instance, or PD_CORE_L). Are you >> planning to add those in a followon patch? > that reminds me, nodes with a reg property should have the base address in > the node name as well. Using the constant works nicely, as can be seen on > the rk3288 where we have for example: > > pd_vio@RK3288_PD_VIO Agreed. > > > Heiko > > > -- caesar wang | software engineer | wxt@rock-chip.com From mboxrd@z Thu Jan 1 00:00:00 1970 From: Caesar Wang Subject: Re: [PATCH] arm64: dts: rockchip: add the power domain node for rk3399 Date: Fri, 01 Jul 2016 10:11:24 +0800 Message-ID: <5775D14C.5040808@rock-chips.com> References: <1467251760-14695-1-git-send-email-wxt@rock-chips.com> <2709691.LCsUme3dJo@phil> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <2709691.LCsUme3dJo@phil> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Heiko Stuebner , Doug Anderson Cc: huangtao , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , Elaine Zhang , Brian Norris , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "open list:ARM/Rockchip SoC..." , Xu Jianqun , "linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" List-Id: devicetree@vger.kernel.org VGhhbmtzIHlvdXIgcmV2aWV3aW5nIQoKT24gMjAxNuW5tDA35pyIMDHml6UgMDU6NTcsIEhlaWtv IFN0dWVibmVyIHdyb3RlOgo+IEFtIERvbm5lcnN0YWcsIDMwLiBKdW5pIDIwMTYsIDE0OjQ5OjQx IHNjaHJpZWIgRG91ZyBBbmRlcnNvbjoKPj4gQ2Flc2FyLAo+Pgo+PiBPbiBXZWQsIEp1biAyOSwg MjAxNiBhdCA2OjU2IFBNLCBDYWVzYXIgV2FuZyA8d3h0QHJvY2stY2hpcHMuY29tPiB3cm90ZToK Pj4+IEZyb206IEVsYWluZSBaaGFuZyA8emhhbmdxaW5nQHJvY2stY2hpcHMuY29tPgo+Pj4KPj4+ IEluIG9yZGVyIHRvIG1lZXQgbG93IHBvd2VyIHJlcXVpcmVtZW50cywgYSBwb3dlciBtYW5hZ2Vt ZW50IHVuaXQgKFBNVSkKPj4+IGlzCj4+PiBkZXNpZ25lZCBmb3IgY29udHJvbGxpbmcgcG93ZXIg cmVzb3VyY2VzIGluIFJLMzM5OS4gVGhlIFJLMzM5OSBQTVUgaXMKPj4+IGRlZGljYXRlZCBmb3Ig bWFuYWdpbmcgdGhlIHBvd2VyIG9mIHRoZSB3aG9sZSBjaGlwLgo+Pj4KPj4+IDEuIGFkZCBwZCBu b2RlIGZvciBSSzMzOTkgU29jCj4+PiAyLiBjcmVhdGUgcG93ZXIgZG9tYWluIHRyZWUKPj4+IDMu IGFkZCBxb3Mgbm9kZSBmb3IgZG9tYWluCj4+Pgo+Pj4gIEZyb20gdGhlIERUL2JpbmRzIGFuZCBk cml2ZXIgY2FuIGdldCBtb3JlIGRldGFpbCBpbmZvcm1hdGlvbjoKPj4+IFRoZSBkcml2ZXI6Cj4+ PiBkcml2ZXJzL3NvYy9yb2NrY2hpcC9wbV9kb21haW5zLmMKPj4+IFRoZSBkb2N1bWVudDoKPj4+ IERvY3VtZW50YXRpb24vZGV2aWNldHJlZS9iaW5kaW5ncy9zb2Mvcm9ja2NoaXAvcG93ZXJfZG9t YWluLnR4dAo+Pj4KPj4+IC0tLQo+Pj4KPj4+IFRlc3RlZCBvbiB2b3AgYW5kIGdwdSBkZXZpY2Vz IGFkZGVkIGZvciBuZXh0IGtlcm5lbC4KPj4+IFBEOgo+Pj4gbG9jYWxob3N0IC8gIyBjYXQgc3lz L2tlcm5lbC9kZWJ1Zy9wbV9nZW5wZC9wbV9nZW5wZF9zdW1tYXJ5Cj4+IE5pdDogY2FuIHlvdSBw dXQgYSAiLyIgYmVmb3JlICJzeXMiIGhlcmUgYW5kIGVsc2V3aGVyZSBpbiB5b3VyIHBhdGNoZXM/ Cj4+Cj4+PiBkb21haW4gICAgICAgICAgICAgICAgICAgICAgICAgIHN0YXR1cyAgICAgICAgICBz bGF2ZXMKPj4+IC9kZXZpY2UgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICBydW50aW1lIHN0YXR1cwo+Pj4gLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLQo+Pj4gcGRfZ3B1ICAgICAgICAg ICAgICAgICAgICAgICAgICBvbgo+Pj4gL2RldmljZXMvcGxhdGZvcm0vZmY5YTAwMDAuZ3B1ICAg ICAgICAgICAgICAgICAgICAgIGFjdGl2ZQo+Pj4gcGRfdm9wbCAgICAgICAgICAgICAgICAgICAg ICAgICBvZmYKPj4+IC9kZXZpY2VzL3BsYXRmb3JtL2ZmOGYwMDAwLnZvcCAgICAgICAgICAgICAg ICAgICAgICBzdXNwZW5kZWQKPj4+IHBkX3ZvcGIgICAgICAgICAgICAgICAgICAgICAgICAgb2Zm Cj4+PiAvZGV2aWNlcy9wbGF0Zm9ybS9mZjkwMDAwMC52b3AgICAgICAgICAgICAgICAgICAgICAg c3VzcGVuZGVkCj4+PiBwZF92byAgICAgICAgICAgICAgICAgICAgICAgICAgIG9mZiAgICAgICAg ICAgICBwZF92b3BiLCBwZF92b3BsCj4+PiBwZF9oZGNwICAgICAgICAgICAgICAgICAgICAgICAg IG9mZgo+Pj4gLi4uCj4+PiBwZF9pZXAgICAgICAgICAgICAgICAgICAgICAgICAgIG9mZgo+Pj4g cGRfdmNvZGVjICAgICAgICAgICAgICAgICAgICAgICBvZmYKPj4+IHBkX3ZkdSAgICAgICAgICAg ICAgICAgICAgICAgICAgb2ZmCj4+Pgo+Pj4gUU9TOgo+Pj4gbG9jYWxob3N0IC8gIyBjYXQgc3lz L2tlcm5lbC9kZWJ1Zy9wbV9xb3MvCj4+PiBjcHVfZG1hX2xhdGVuY3kgICAgIG5ldHdvcmtfbGF0 ZW5jeQo+Pj4gbWVtb3J5X2JhbmR3aWR0aCAgICBuZXR3b3JrX3Rocm91Z2hwdXQKPj4gV2hhdCBp cyB0aGlzIHN1cHBvc2VkIHRvIGJlIHNob3dpbmcgZXhhY3RseT8gIFlvdSBjYW4ndCAiY2F0IiBh Cj4+IGRpcmVjdG9yeSwgc28gbWF5YmUgeW91IG1lYW50ICJscyI/Cj4+Cj4+IEFsc28sIGVhY2gg b2YgdGhlc2UgZmlsZXMgY29udGFpbnMgdGhlIHN0cmluZyAiRW1wdHkhIiBhbmQgdGhlc2UgZmls ZXMKPj4gc2VlbSBmYWlybHkgdW5jb25uZWN0ZWQgdG8geW91ciBwYXRjaC4gIFRob3NlIGZpbGVz IGV4aXN0IGJvdGggYmVmb3JlCj4+IGFuZCBhZnRlciB5b3VyIHBhdGNoIGFuZCBub3RoaW5nIHRo YXQgSSBjYW4gc2VlIGluIHRoZSBSb2NrY2hpcCBRb1MKPj4gc3R1ZmYgaG9va3MgdXAgdG8gdGhl IGdlbmVyaWMgTGludXggUW9TIGluZnJhc3RydWN0dXJlLiAgVGhlIHBvd2VyCj4+IGRvbWFpbnMg anVzdCBzYXZlIGFuZCByZXN0b3JlIHRoZSBRb1MtLXRoZXkgZG9uJ3QgYWN0dWFsbHkgYWxsb3cK Pj4gc2V0dHRpbmcgaXQuCj4gcGVyc29uYWxseSwgSSB3b3VsZCBqdXN0IGRyb3AgdGhhdCBkZWJ1 Z2ZzLWR1bXAsIGFzIEkgZG9uJ3Qgc2VlIHdoYXQgd2UgZ2Fpbgo+IGZyb20gaXQgOi0pLgoKQWdy ZWVkLCBkcm9wIGl0LgoKPj4+IFNpZ25lZC1vZmYtYnk6IEVsYWluZSBaaGFuZyA8emhhbmdxaW5n QHJvY2stY2hpcHMuY29tPgo+Pj4gU2lnbmVkLW9mZi1ieTogQ2Flc2FyIFdhbmcgPHd4dEByb2Nr LWNoaXBzLmNvbT4KPj4+IC0tLQo+IFsuLi5dCj4KPj4+ICsgICAgICAgcG11OiBwb3dlci1tYW5h Z2VtZW50QGZmMzEwMDAwIHsKPj4+ICsgICAgICAgICAgICAgICBjb21wYXRpYmxlID0gInJvY2tj aGlwLHJrMzM5OS1wbXUiLCAic3lzY29uIiwKPj4+ICJzaW1wbGUtbWZkIjsgKyAgICAgICAgICAg ICAgIHJlZyA9IDwweDAgMHhmZjMxMDAwMCAweDAgMHgxMDAwPjsKPj4+ICsKPj4+ICsgICAgICAg ICAgICAgICBwb3dlcjogcG93ZXItY29udHJvbGxlciB7Cj4+PiArICAgICAgICAgICAgICAgICAg ICAgICBzdGF0dXMgPSAib2theSI7Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICBjb21wYXRp YmxlID0gInJvY2tjaGlwLHJrMzM5OS1wb3dlci1jb250cm9sbGVyIjsKPj4+ICsgICAgICAgICAg ICAgICAgICAgICAgICNwb3dlci1kb21haW4tY2VsbHMgPSA8MT47Cj4+PiArICAgICAgICAgICAg ICAgICAgICAgICAjYWRkcmVzcy1jZWxscyA9IDwxPjsKPj4+ICsgICAgICAgICAgICAgICAgICAg ICAgICNzaXplLWNlbGxzID0gPDA+Owo+Pj4gKwo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAg cGRfdmR1IHsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcmVnID0gPFJLMzM5 OV9QRF9WRFU+Owo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBjbG9ja3MgPSA8 JmNydSBBQ0xLX1ZEVT4sCj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgIDwmY3J1IEhDTEtfVkRVPjsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg cG1fcW9zID0gPCZxb3NfdmlkZW9fbTFfcj4sCj4+PiArICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIDwmcW9zX3ZpZGVvX20xX3c+Owo+Pj4gKyAgICAgICAgICAgICAgICAg ICAgICAgfTsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgIHBkX3Zjb2RlYyB7Cj4+PiArICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJlZyA9IDxSSzMzOTlfUERfVkNPREVDPjsKPj4+ ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgY2xvY2tzID0gPCZjcnUgQUNMS19WQ09E RUM+LAo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICA8JmNydSBI Q0xLX1ZDT0RFQz47Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHBtX3FvcyA9 IDwmcW9zX3ZpZGVvX20wPjsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgIH07Cj4+PiArICAg ICAgICAgICAgICAgICAgICAgICBwZF9pZXAgewo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICByZWcgPSA8UkszMzk5X1BEX0lFUD47Cj4+PiArICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIGNsb2NrcyA9IDwmY3J1IEFDTEtfSUVQPiwKPj4+ICsgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgPCZjcnUgSENMS19JRVA+Owo+Pj4gKyAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICBwbV9xb3MgPSA8JnFvc19pZXA+Owo+Pj4gKyAgICAgICAgICAg ICAgICAgICAgICAgfTsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgIHBkX3JnYSB7Cj4+PiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHJlZyA9IDxSSzMzOTlfUERfUkdBPjsKPj4+ ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgY2xvY2tzID0gPCZjcnUgQUNMS19SR0E+ LAo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICA8JmNydSBIQ0xL X1JHQT47Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHBtX3FvcyA9IDwmcW9z X3JnYV9yPiwKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgPCZx b3NfcmdhX3c+Owo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgfTsKPj4+ICsgICAgICAgICAg ICAgICAgICAgICAgIHBkX3ZpbyB7Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg IHJlZyA9IDxSSzMzOTlfUERfVklPPjsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgI2FkZHJlc3MtY2VsbHMgPSA8MT47Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICNzaXplLWNlbGxzID0gPDA+Owo+Pj4gKwo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICBwZF9pc3AwIHsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICByZWcgPSA8UkszMzk5X1BEX0lTUDA+Owo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIGNsb2NrcyA9IDwmY3J1IEFDTEtfSVNQMD4sCj4+PiArICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgPCZjcnUgSENMS19JU1AwPjsK Pj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBwbV9xb3MgPSA8JnFv c19pc3AwX20wPiwKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICA8JnFvc19pc3AwX20xPjsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgfTsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcGRfaXNwMSB7Cj4+PiAr ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcmVnID0gPFJLMzM5OV9QRF9J U1AxPjsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBjbG9ja3Mg PSA8JmNydSBBQ0xLX0lTUDE+LAo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIDwmY3J1IEhDTEtfSVNQMT47Cj4+PiArICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgcG1fcW9zID0gPCZxb3NfaXNwMV9tMD4sCj4+PiArICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgPCZxb3NfaXNwMV9tMT47 Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIH07Cj4+PiArICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgIHBkX2hkY3Agewo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgIHJlZyA9IDxSSzMzOTlfUERfSERDUD47Cj4+PiArICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgY2xvY2tzID0gPCZjcnUgQUNMS19IRENQPiwKPj4+ ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICA8JmNydSBI Q0xLX0hEQ1A+LAo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgIDwmY3J1IFBDTEtfSERDUD47Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgcG1fcW9zID0gPCZxb3NfaGRjcD47Cj4+PiArICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgIH07Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgIHBkX3Zv IHsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICByZWcgPSA8Uksz Mzk5X1BEX1ZPPjsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAj YWRkcmVzcy1jZWxscyA9IDwxPjsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAjc2l6ZS1jZWxscyA9IDwwPjsKPj4+ICsKPj4+ICsgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICBwZF92b3BiIHsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgIHJlZyA9IDxSSzMzOTlfUERfVk9QQj47Cj4+PiArICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBjbG9ja3MgPSA8JmNy dQo+Pj4gQUNMS19WT1AwPiwgKwo+Pj4gPCZjcnUgSENMS19WT1AwPjsgKwo+Pj4gcG1fcW9zID0g PCZxb3Nfdm9wX2JpZ19yPiwgKwo+Pj4gICAgICAgICAgICAgIDwmcW9zX3ZvcF9iaWdfdz47ICsK Pj4+IH07Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgcGRfdm9w bCB7Cj4+PiArICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICBy ZWcgPSA8UkszMzk5X1BEX1ZPUEw+Owo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgICAgY2xvY2tzID0gPCZjcnUKPj4+IEFDTEtfVk9QMT4sICsKPj4+IDwm Y3J1IEhDTEtfVk9QMT47ICsKPj4+IHBtX3FvcyA9IDwmcW9zX3ZvcF9saXR0bGU+OyArICAgICAg ICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgICAgfTsKPj4+ICsgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgfTsKPj4+ICsgICAgICAgICAgICAgICAgICAgICAgIH07Cj4+PiArICAg ICAgICAgICAgICAgICAgICAgICBwZF9ncHUgewo+Pj4gKyAgICAgICAgICAgICAgICAgICAgICAg ICAgICAgICByZWcgPSA8UkszMzk5X1BEX0dQVT47Cj4+PiArICAgICAgICAgICAgICAgICAgICAg ICAgICAgICAgIGNsb2NrcyA9IDwmY3J1IEFDTEtfR1BVPjsKPj4+ICsgICAgICAgICAgICAgICAg ICAgICAgICAgICAgICAgcG1fcW9zID0gPCZxb3NfZ3B1PjsKPj4+ICsgICAgICAgICAgICAgICAg ICAgICAgIH07Cj4+IEFnYWluIGEgbml0dHkgc29ydCBvcmRlciBxdWVzdGlvbi4gIElzIHRoZXJl IGEgcmVhc29uIG5vdCB0byBtYWtlCj4+IHRoaW5ncyBhbHBoYWJldGljYWw/ICBBS0E6IHBkX2dw dSwgcGRfaWVwLCBwZF9yZ2EsIC4uLgo+Pgo+PiAuLi5hbmQgaW5zaWRlIHBkX3ZpbyBzaG91bGQg YmUgYWxwaGFiZXRpY2FsIHRvbz8KPj4KPj4gSW4gdGhlIFRSTSBpdCBsb29rcyBsaWtlIHNvbWUg b2YgdGhlIHBvd2VyIGRvbWFpbnMgYXJlIGdyb3VwZWQKPj4gdG9nZXRoZXIgKGxpa2UgYWxsIHRo ZSBkb21haW5zIHVuZGVyIExPR0lDIG9yIENFTlRFUkxPR0lDKS4gIElmCj4+IGtlZXBpbmcgdGhh dCBncm91cGluZyBtYWtlcyBzZW5zZSBoZXJlIHRoZW4geW91IHNob3VsZCBhZGQgYSBjb21tZW50 Cj4+IGF0IHRoZSBzdGFydCBvZiBlYWNoIGdyb3VwIGFuZCBzb3J0IHRoZSBncm91cHMgc2FuZWx5 IChhbmQgc29ydCB3aXRoaW4KPj4gZWFjaCBncm91cCkuCgpPa2F5LCBsZXQgbWUgc2VlIGl0LgoK VGhhbmtzIQoKPj4KPj4gSXQgbG9va3MgbGlrZSB0aGVyZSBhcmUgYWxzbyBtb3JlIHBvd2VyIGRv bWFpbnMgdGhhdCB5b3UgaGF2ZW4ndAo+PiBsaXN0ZWQgaGVyZSAobGlrZSBQRF9HTUFDLCBmb3Ig aW5zdGFuY2UsIG9yIFBEX0NPUkVfTCkuICBBcmUgeW91Cj4+IHBsYW5uaW5nIHRvIGFkZCB0aG9z ZSBpbiBhIGZvbGxvd29uIHBhdGNoPwo+IHRoYXQgcmVtaW5kcyBtZSwgbm9kZXMgd2l0aCBhIHJl ZyBwcm9wZXJ0eSBzaG91bGQgaGF2ZSB0aGUgYmFzZSBhZGRyZXNzIGluCj4gdGhlIG5vZGUgbmFt ZSBhcyB3ZWxsLiBVc2luZyB0aGUgY29uc3RhbnQgd29ya3MgbmljZWx5LCBhcyBjYW4gYmUgc2Vl biBvbgo+IHRoZSByazMyODggd2hlcmUgd2UgaGF2ZSBmb3IgZXhhbXBsZToKPgo+IAlwZF92aW9A UkszMjg4X1BEX1ZJTwoKQWdyZWVkLgoKCj4KPgo+IEhlaWtvCj4KPgo+CgotLSAKY2Flc2FyIHdh bmcgfCBzb2Z0d2FyZSBlbmdpbmVlciB8IHd4dEByb2NrLWNoaXAuY29tCgoKCl9fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCkxpbnV4LXJvY2tjaGlwIG1haWxp bmcgbGlzdApMaW51eC1yb2NrY2hpcEBsaXN0cy5pbmZyYWRlYWQub3JnCmh0dHA6Ly9saXN0cy5p bmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgtcm9ja2NoaXAK From mboxrd@z Thu Jan 1 00:00:00 1970 From: wxt@rock-chips.com (Caesar Wang) Date: Fri, 01 Jul 2016 10:11:24 +0800 Subject: [PATCH] arm64: dts: rockchip: add the power domain node for rk3399 In-Reply-To: <2709691.LCsUme3dJo@phil> References: <1467251760-14695-1-git-send-email-wxt@rock-chips.com> <2709691.LCsUme3dJo@phil> Message-ID: <5775D14C.5040808@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Thanks your reviewing! On 2016?07?01? 05:57, Heiko Stuebner wrote: > Am Donnerstag, 30. Juni 2016, 14:49:41 schrieb Doug Anderson: >> Caesar, >> >> On Wed, Jun 29, 2016 at 6:56 PM, Caesar Wang wrote: >>> From: Elaine Zhang >>> >>> In order to meet low power requirements, a power management unit (PMU) >>> is >>> designed for controlling power resources in RK3399. The RK3399 PMU is >>> dedicated for managing the power of the whole chip. >>> >>> 1. add pd node for RK3399 Soc >>> 2. create power domain tree >>> 3. add qos node for domain >>> >>> From the DT/binds and driver can get more detail information: >>> The driver: >>> drivers/soc/rockchip/pm_domains.c >>> The document: >>> Documentation/devicetree/bindings/soc/rockchip/power_domain.txt >>> >>> --- >>> >>> Tested on vop and gpu devices added for next kernel. >>> PD: >>> localhost / # cat sys/kernel/debug/pm_genpd/pm_genpd_summary >> Nit: can you put a "/" before "sys" here and elsewhere in your patches? >> >>> domain status slaves >>> /device runtime status >>> ---------------------------------------------------------------------- >>> pd_gpu on >>> /devices/platform/ff9a0000.gpu active >>> pd_vopl off >>> /devices/platform/ff8f0000.vop suspended >>> pd_vopb off >>> /devices/platform/ff900000.vop suspended >>> pd_vo off pd_vopb, pd_vopl >>> pd_hdcp off >>> ... >>> pd_iep off >>> pd_vcodec off >>> pd_vdu off >>> >>> QOS: >>> localhost / # cat sys/kernel/debug/pm_qos/ >>> cpu_dma_latency network_latency >>> memory_bandwidth network_throughput >> What is this supposed to be showing exactly? You can't "cat" a >> directory, so maybe you meant "ls"? >> >> Also, each of these files contains the string "Empty!" and these files >> seem fairly unconnected to your patch. Those files exist both before >> and after your patch and nothing that I can see in the Rockchip QoS >> stuff hooks up to the generic Linux QoS infrastructure. The power >> domains just save and restore the QoS--they don't actually allow >> settting it. > personally, I would just drop that debugfs-dump, as I don't see what we gain > from it :-). Agreed, drop it. >>> Signed-off-by: Elaine Zhang >>> Signed-off-by: Caesar Wang >>> --- > [...] > >>> + pmu: power-management at ff310000 { >>> + compatible = "rockchip,rk3399-pmu", "syscon", >>> "simple-mfd"; + reg = <0x0 0xff310000 0x0 0x1000>; >>> + >>> + power: power-controller { >>> + status = "okay"; >>> + compatible = "rockchip,rk3399-power-controller"; >>> + #power-domain-cells = <1>; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + pd_vdu { >>> + reg = ; >>> + clocks = <&cru ACLK_VDU>, >>> + <&cru HCLK_VDU>; >>> + pm_qos = <&qos_video_m1_r>, >>> + <&qos_video_m1_w>; >>> + }; >>> + pd_vcodec { >>> + reg = ; >>> + clocks = <&cru ACLK_VCODEC>, >>> + <&cru HCLK_VCODEC>; >>> + pm_qos = <&qos_video_m0>; >>> + }; >>> + pd_iep { >>> + reg = ; >>> + clocks = <&cru ACLK_IEP>, >>> + <&cru HCLK_IEP>; >>> + pm_qos = <&qos_iep>; >>> + }; >>> + pd_rga { >>> + reg = ; >>> + clocks = <&cru ACLK_RGA>, >>> + <&cru HCLK_RGA>; >>> + pm_qos = <&qos_rga_r>, >>> + <&qos_rga_w>; >>> + }; >>> + pd_vio { >>> + reg = ; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + pd_isp0 { >>> + reg = ; >>> + clocks = <&cru ACLK_ISP0>, >>> + <&cru HCLK_ISP0>; >>> + pm_qos = <&qos_isp0_m0>, >>> + <&qos_isp0_m1>; >>> + }; >>> + pd_isp1 { >>> + reg = ; >>> + clocks = <&cru ACLK_ISP1>, >>> + <&cru HCLK_ISP1>; >>> + pm_qos = <&qos_isp1_m0>, >>> + <&qos_isp1_m1>; >>> + }; >>> + pd_hdcp { >>> + reg = ; >>> + clocks = <&cru ACLK_HDCP>, >>> + <&cru HCLK_HDCP>, >>> + <&cru PCLK_HDCP>; >>> + pm_qos = <&qos_hdcp>; >>> + }; >>> + pd_vo { >>> + reg = ; >>> + #address-cells = <1>; >>> + #size-cells = <0>; >>> + >>> + pd_vopb { >>> + reg = ; >>> + clocks = <&cru >>> ACLK_VOP0>, + >>> <&cru HCLK_VOP0>; + >>> pm_qos = <&qos_vop_big_r>, + >>> <&qos_vop_big_w>; + >>> }; >>> + pd_vopl { >>> + reg = ; >>> + clocks = <&cru >>> ACLK_VOP1>, + >>> <&cru HCLK_VOP1>; + >>> pm_qos = <&qos_vop_little>; + }; >>> + }; >>> + }; >>> + pd_gpu { >>> + reg = ; >>> + clocks = <&cru ACLK_GPU>; >>> + pm_qos = <&qos_gpu>; >>> + }; >> Again a nitty sort order question. Is there a reason not to make >> things alphabetical? AKA: pd_gpu, pd_iep, pd_rga, ... >> >> ...and inside pd_vio should be alphabetical too? >> >> In the TRM it looks like some of the power domains are grouped >> together (like all the domains under LOGIC or CENTERLOGIC). If >> keeping that grouping makes sense here then you should add a comment >> at the start of each group and sort the groups sanely (and sort within >> each group). Okay, let me see it. Thanks! >> >> It looks like there are also more power domains that you haven't >> listed here (like PD_GMAC, for instance, or PD_CORE_L). Are you >> planning to add those in a followon patch? > that reminds me, nodes with a reg property should have the base address in > the node name as well. Using the constant works nicely, as can be seen on > the rk3288 where we have for example: > > pd_vio at RK3288_PD_VIO Agreed. > > > Heiko > > > -- caesar wang | software engineer | wxt at rock-chip.com