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From: Russ Weight <russell.h.weight@intel.com>
To: Tom Rix <trix@redhat.com>,
	mdf@kernel.org, lee.jones@linaro.org, linux-fpga@vger.kernel.org,
	linux-kernel@vger.kernel.org
Cc: lgoncalv@redhat.com, yilun.xu@intel.com, hao.wu@intel.com,
	matthew.gerlach@intel.com
Subject: Re: [PATCH v1 12/12] fpga: add max10 get_hw_errinfo callback func
Date: Thu, 24 Sep 2020 14:48:26 -0700	[thread overview]
Message-ID: <59ef7ab5-87be-3c5a-bee1-8bb165e69e48@intel.com> (raw)
In-Reply-To: <b90e8435-651c-e901-8be3-b0dac6eaac22@redhat.com>



On 9/6/20 10:14 AM, Tom Rix wrote:
> On 9/4/20 4:53 PM, Russ Weight wrote:
>> Extend the MAX10 BMC Security Engine driver to include
>> a function that returns 64 bits of additional HW specific
>> data for errors that require additional information.
>> This callback function enables the hw_errinfo sysfs
>> node in the Intel Security Manager class driver.
>>
>> Signed-off-by: Russ Weight <russell.h.weight@intel.com>
>> Reviewed-by: Wu Hao <hao.wu@intel.com>
>> ---
>>  drivers/fpga/intel-m10-bmc-secure.c | 27 ++++++++++++++++++++++++++-
>>  1 file changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/fpga/intel-m10-bmc-secure.c b/drivers/fpga/intel-m10-bmc-secure.c
>> index 4a66c2d448eb..7fb1c805f654 100644
>> --- a/drivers/fpga/intel-m10-bmc-secure.c
>> +++ b/drivers/fpga/intel-m10-bmc-secure.c
>> @@ -450,6 +450,30 @@ static enum ifpga_sec_err m10bmc_sec_cancel(struct ifpga_sec_mgr *imgr)
>>  	return ret ? IFPGA_SEC_ERR_RW_ERROR : IFPGA_SEC_ERR_NONE;
>>  }
>>  
>> +static u64 m10bmc_sec_hw_errinfo(struct ifpga_sec_mgr *imgr)
>> +{
>> +	struct m10bmc_sec *sec = imgr->priv;
>> +	u32 doorbell = 0, auth_result = 0;
>> +	u64 hw_errinfo = 0;
> hw_errinfo should be initialized to some poison value like -1
>
> to cover the case if either of sys_read's fail.
Yes - that is a good idea. I'll make a change for the next patch version.

- Russ
>
> Tom
>
>> +
>> +	switch (imgr->err_code) {
>> +	case IFPGA_SEC_ERR_HW_ERROR:
>> +	case IFPGA_SEC_ERR_TIMEOUT:
>> +	case IFPGA_SEC_ERR_BUSY:
>> +	case IFPGA_SEC_ERR_WEAROUT:
>> +		if (!m10bmc_sys_read(sec->m10bmc, M10BMC_DOORBELL, &doorbell))
>> +			hw_errinfo = (u64)doorbell << 32;
>> +
>> +		if (!m10bmc_sys_read(sec->m10bmc, M10BMC_AUTH_RESULT,
>> +				     &auth_result))
>> +			hw_errinfo |= (u64)auth_result;
>> +
>> +		return hw_errinfo;
>> +	default:
>> +		return 0;
>> +	}
>> +}
>> +
>>  static const struct ifpga_sec_mgr_ops m10bmc_iops = {
>>  	.user_flash_count = get_qspi_flash_count,
>>  	.bmc_root_entry_hash = get_bmc_root_entry_hash,
>> @@ -467,7 +491,8 @@ static const struct ifpga_sec_mgr_ops m10bmc_iops = {
>>  	.prepare = m10bmc_sec_prepare,
>>  	.write_blk = m10bmc_sec_write_blk,
>>  	.poll_complete = m10bmc_sec_poll_complete,
>> -	.cancel = m10bmc_sec_cancel
>> +	.cancel = m10bmc_sec_cancel,
>> +	.get_hw_errinfo = m10bmc_sec_hw_errinfo
>>  };
>>  
>>  static void ifpga_sec_mgr_uinit(struct m10bmc_sec *sec)


  reply	other threads:[~2020-09-24 21:48 UTC|newest]

Thread overview: 57+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-09-04 23:52 [PATCH v1 00/12] Intel FPGA Security Manager Class Driver Russ Weight
2020-09-04 23:52 ` [PATCH v1 01/12] fpga: fpga security manager class driver Russ Weight
2020-09-04 23:57   ` Randy Dunlap
2020-09-05  0:23   ` Moritz Fischer
2020-09-05  0:44     ` Russ Weight
2020-09-05 13:39       ` Wu, Hao
2020-09-05 19:09   ` Tom Rix
     [not found]     ` <ebf251a0-5f13-d1a1-6915-e3c940bb19fe@intel.com>
2020-09-10 21:51       ` Tom Rix
2020-09-10 23:05         ` Russ Weight
2020-09-16 20:16   ` Moritz Fischer
2020-09-30 20:54     ` Russ Weight
2020-10-01  0:31       ` Moritz Fischer
2020-10-01  1:07         ` Russ Weight
2020-10-01 19:07           ` Moritz Fischer
2020-09-04 23:52 ` [PATCH v1 02/12] fpga: create intel max10 bmc security engine Russ Weight
2020-09-05  0:01   ` Randy Dunlap
2020-09-05  0:05     ` Russ Weight
2020-09-05 20:22   ` Tom Rix
2020-09-14 19:07     ` Russ Weight
2020-09-14 20:48       ` Tom Rix
2020-09-14 21:40         ` Russ Weight
2020-09-16 20:33   ` Moritz Fischer
2020-09-30 23:14     ` Russ Weight
2020-09-04 23:52 ` [PATCH v1 03/12] fpga: expose max10 flash update counts in sysfs Russ Weight
2020-09-05 20:39   ` Tom Rix
2020-09-16 18:37     ` Russ Weight
2020-09-04 23:52 ` [PATCH v1 04/12] fpga: expose max10 canceled keys " Russ Weight
2020-09-05 20:52   ` Tom Rix
2020-09-04 23:52 ` [PATCH v1 05/12] fpga: enable secure updates Russ Weight
2020-09-05 22:04   ` Tom Rix
     [not found]     ` <1d90bfb6-417c-55df-9290-991c391158a9@intel.com>
2020-09-20 15:24       ` Tom Rix
2020-09-04 23:52 ` [PATCH v1 06/12] fpga: add max10 secure update functions Russ Weight
2020-09-06 16:10   ` Tom Rix
2020-09-22  1:15     ` Russ Weight
2020-09-08  8:05   ` Lee Jones
2020-09-04 23:53 ` [PATCH v1 07/12] fpga: expose sec-mgr update status Russ Weight
2020-09-06 16:16   ` Tom Rix
2020-09-22 22:31     ` Russ Weight
2020-09-04 23:53 ` [PATCH v1 08/12] fpga: expose sec-mgr update errors Russ Weight
2020-09-06 16:27   ` Tom Rix
2020-09-22 23:42     ` Russ Weight
2020-09-23 12:52       ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 09/12] fpga: expose sec-mgr update size Russ Weight
2020-09-06 16:39   ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 10/12] fpga: enable sec-mgr update cancel Russ Weight
2020-09-06 17:00   ` Tom Rix
     [not found]     ` <678f8d39-a244-42d0-4c56-91eb859b43f0@intel.com>
2020-09-23 13:02       ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 11/12] fpga: expose hardware error info in sysfs Russ Weight
2020-09-06 17:06   ` Tom Rix
2020-09-04 23:53 ` [PATCH v1 12/12] fpga: add max10 get_hw_errinfo callback func Russ Weight
2020-09-06 17:14   ` Tom Rix
2020-09-24 21:48     ` Russ Weight [this message]
2020-09-05 14:13 ` [PATCH v1 00/12] Intel FPGA Security Manager Class Driver Wu, Hao
2020-10-01 20:42   ` Russ Weight
2020-09-05 16:10 ` Tom Rix
2020-09-05 17:16 ` Tom Rix
2020-10-01  0:19   ` Russ Weight

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