All of lore.kernel.org
 help / color / mirror / Atom feed
From: Julien Grall <julien.grall@arm.com>
To: "André Przywara" <andre.przywara@arm.com>,
	"Stefano Stabellini" <sstabellini@kernel.org>
Cc: xen-devel@lists.xenproject.org,
	Shanker Donthineni <shankerd@codeaurora.org>,
	Vijay Kilari <vijay.kilari@gmail.com>
Subject: Re: [PATCH v2 04/27] ARM: GICv3 ITS: map ITS command buffer
Date: Wed, 22 Mar 2017 16:41:54 +0000	[thread overview]
Message-ID: <6b4d3c2e-784b-a6c9-6dda-06ba85ad8471@arm.com> (raw)
In-Reply-To: <0792dfbf-a86f-f4fe-d9cf-076bf53c2745@arm.com>

Hi Andre,

On 22/03/17 16:31, André Przywara wrote:
> On 22/03/17 15:23, Julien Grall wrote:
>> On 16/03/17 11:20, Andre Przywara wrote:
>>> +
>>>  LIST_HEAD(host_its_list);
>>>
>>>  bool gicv3_its_host_has_its(void)
>>> @@ -56,6 +59,55 @@ static uint64_t encode_propbaser_phys_addr(paddr_t
>>> addr, unsigned int page_bits)
>>>      return ret | ((addr & GENMASK(51, 48)) >> (48 - 12));
>>>  }
>>>
>>> +static void *its_map_cbaser(struct host_its *its)
>>> +{
>>> +    void __iomem *cbasereg = its->its_base + GITS_CBASER;
>>> +    uint64_t reg;
>>> +    void *buffer;
>>> +    unsigned int order;
>>> +
>>> +    reg  = GIC_BASER_InnerShareable << GITS_BASER_SHAREABILITY_SHIFT;
>>> +    reg |= GIC_BASER_CACHE_SameAsInner <<
>>> GITS_BASER_OUTER_CACHEABILITY_SHIFT;
>>> +    reg |= GIC_BASER_CACHE_RaWaWb <<
>>> GITS_BASER_INNER_CACHEABILITY_SHIFT;
>>> +
>>> +    /* The ITS command buffer needs to be 64K aligned. */
>>
>> Looking at the spec, the command buffer does not need to be 64K aligned.
>> On the previous version, you made it 4K aligned. So why this restriction?
>
> As you have already learnt, the GIC is more subtle sometimes ;-) Read
> the description at "Physical_Address, bits [51:12]" in the CBASER
> paragraph and tell me what you take from it. I decided to read it as
> "has to be 64K aligned".
> Happy to correct this otherwise.

Hmmm. I think you are right. This is a little bit weird, but fine. Lets 
keep like that.

>
>>> +    order = max(get_order_from_bytes(ITS_CMD_QUEUE_SZ), 16U -
>>> PAGE_SHIFT);
>>> +    buffer = alloc_xenheap_pages(order, 0);
>>
>> I am not sure to understand why you move from _zalloc to
>> alloc_xenheap_*. The resulting behavior will be exactly the same but the
>> former result to a simpler code.
>                                                   ^^^^^^^^^^^^^^^^
> Really?
> I checked and found that alloc_xenheap_pages gives me physically
> contiguous allocation in the given order, where *alloc just guarantees
> virtually contiguous pages.

Yes. Give a look at my answer on patch #3.

Regards,

-- 
Julien Grall

_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xen.org
https://lists.xen.org/xen-devel

  reply	other threads:[~2017-03-22 16:41 UTC|newest]

Thread overview: 119+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-16 11:20 [PATCH v2 00/27] arm64: Dom0 ITS emulation Andre Przywara
2017-03-16 11:20 ` [PATCH v2 01/27] ARM: GICv3 ITS: parse and store ITS subnodes from hardware DT Andre Przywara
2017-03-21 20:17   ` Julien Grall
2017-03-23 10:57     ` Andre Przywara
2017-03-23 17:32       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 02/27] ARM: GICv3: allocate LPI pending and property table Andre Przywara
2017-03-21 21:23   ` Julien Grall
2017-03-23 14:40     ` Andre Przywara
2017-03-23 17:42       ` Julien Grall
2017-03-23 17:45         ` Stefano Stabellini
2017-03-23 17:49           ` Julien Grall
2017-03-23 18:01             ` Stefano Stabellini
2017-03-23 18:21               ` Andre Przywara
2017-03-24 11:45                 ` Julien Grall
2017-03-24 17:22                   ` Stefano Stabellini
2017-03-21 22:57   ` Stefano Stabellini
2017-03-21 23:08     ` André Przywara
2017-03-21 23:27       ` Stefano Stabellini
2017-03-23 10:50         ` Andre Przywara
2017-03-23 17:47           ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 03/27] ARM: GICv3 ITS: allocate device and collection table Andre Przywara
2017-03-21 23:29   ` Stefano Stabellini
2017-03-22 13:52   ` Julien Grall
2017-03-22 16:08     ` André Przywara
2017-03-22 16:33       ` Julien Grall
2017-03-29 13:58         ` Andre Przywara
2017-03-16 11:20 ` [PATCH v2 04/27] ARM: GICv3 ITS: map ITS command buffer Andre Przywara
2017-03-21 23:48   ` Stefano Stabellini
2017-03-22 15:23   ` Julien Grall
2017-03-22 16:31     ` André Przywara
2017-03-22 16:41       ` Julien Grall [this message]
2017-03-16 11:20 ` [PATCH v2 05/27] ARM: GICv3 ITS: introduce ITS command handling Andre Przywara
2017-03-16 15:05   ` Shanker Donthineni
2017-03-16 15:18     ` Andre Przywara
2017-03-22  0:02   ` Stefano Stabellini
2017-03-22 15:59   ` Julien Grall
2017-04-03 10:58     ` Andre Przywara
2017-04-03 11:23       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 06/27] ARM: GICv3 ITS: introduce device mapping Andre Przywara
2017-03-22 17:29   ` Julien Grall
2017-04-03 20:08     ` Andre Przywara
2017-04-03 20:41       ` Julien Grall
2017-04-04  9:57         ` Andre Przywara
2017-03-22 22:45   ` Stefano Stabellini
2017-04-03 19:45     ` Andre Przywara
2017-03-30 11:17   ` Vijay Kilari
2017-03-16 11:20 ` [PATCH v2 07/27] ARM: arm64: activate atomic 64-bit accessors Andre Przywara
2017-03-22 17:30   ` Julien Grall
2017-03-22 22:49     ` Stefano Stabellini
2017-03-16 11:20 ` [PATCH v2 08/27] ARM: GICv3 ITS: introduce host LPI array Andre Przywara
2017-03-22 23:38   ` Stefano Stabellini
2017-03-23  8:48     ` Julien Grall
2017-03-23 10:21     ` Andre Przywara
2017-03-23 17:52       ` Stefano Stabellini
2017-03-24 11:54         ` Julien Grall
2017-03-23 19:08   ` Julien Grall
2017-04-03 19:30     ` Andre Przywara
2017-04-03 20:13       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 09/27] ARM: GICv3: introduce separate pending_irq structs for LPIs Andre Przywara
2017-03-22 23:44   ` Stefano Stabellini
2017-03-23 20:08     ` André Przywara
2017-03-24 10:59       ` Julien Grall
2017-03-24 11:40   ` Julien Grall
2017-03-24 15:50     ` Andre Przywara
2017-03-24 16:19       ` Julien Grall
2017-03-24 17:26       ` Stefano Stabellini
2017-03-27  9:02         ` Andre Przywara
2017-03-27 14:01           ` Julien Grall
2017-03-27 17:44             ` Stefano Stabellini
2017-03-27 17:49               ` Julien Grall
2017-03-27 18:39                 ` Stefano Stabellini
2017-03-27 21:24                   ` Julien Grall
2017-03-28  7:58                   ` Jan Beulich
2017-03-28 13:12                     ` Julien Grall
2017-03-28 13:34                       ` Jan Beulich
2017-03-16 11:20 ` [PATCH v2 10/27] ARM: GICv3: forward pending LPIs to guests Andre Przywara
2017-03-24 12:03   ` Julien Grall
2017-04-03 14:18     ` Andre Przywara
2017-04-04 11:49       ` Julien Grall
2017-04-04 12:51         ` Andre Przywara
2017-04-04 12:50           ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 11/27] ARM: GICv3: enable ITS and LPIs on the host Andre Przywara
2017-03-16 11:20 ` [PATCH v2 12/27] ARM: vGICv3: handle virtual LPI pending and property tables Andre Przywara
2017-03-24 12:09   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 13/27] ARM: vGICv3: Handle disabled LPIs Andre Przywara
2017-03-24 12:20   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 14/27] ARM: vGICv3: introduce basic ITS emulation bits Andre Przywara
2017-03-16 16:25   ` Shanker Donthineni
2017-03-20 12:17     ` Vijay Kilari
2017-03-24 12:41   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 15/27] ARM: vITS: introduce translation table walks Andre Przywara
2017-03-24 13:00   ` Julien Grall
2017-04-03 18:25     ` Andre Przywara
2017-04-04 15:59       ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 16/27] ARM: vITS: handle CLEAR command Andre Przywara
2017-03-24 14:27   ` Julien Grall
2017-03-24 15:53     ` Andre Przywara
2017-03-24 17:17       ` Stefano Stabellini
2017-03-27  8:44         ` Andre Przywara
2017-03-27 14:12           ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 17/27] ARM: vITS: handle INT command Andre Przywara
2017-03-24 14:38   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 18/27] ARM: vITS: handle MAPC command Andre Przywara
2017-03-16 11:20 ` [PATCH v2 19/27] ARM: vITS: handle MAPD command Andre Przywara
2017-03-24 14:41   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 20/27] ARM: vITS: handle MAPTI command Andre Przywara
2017-03-24 14:54   ` Julien Grall
2017-04-03 18:47     ` Andre Przywara
2017-03-16 11:20 ` [PATCH v2 21/27] ARM: vITS: handle MOVI command Andre Przywara
2017-03-24 15:00   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 22/27] ARM: vITS: handle DISCARD command Andre Przywara
2017-03-16 11:20 ` [PATCH v2 23/27] ARM: vITS: handle INV command Andre Przywara
2017-03-16 11:20 ` [PATCH v2 24/27] ARM: vITS: handle INVALL command Andre Przywara
2017-03-24 15:12   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 25/27] ARM: vITS: create and initialize virtual ITSes for Dom0 Andre Przywara
2017-03-24 15:18   ` Julien Grall
2017-03-16 11:20 ` [PATCH v2 26/27] ARM: vITS: create ITS subnodes for Dom0 DT Andre Przywara
2017-03-16 11:20 ` [PATCH v2 27/27] ARM: vGIC: advertise LPI support Andre Przywara
2017-03-24 15:25   ` Julien Grall

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=6b4d3c2e-784b-a6c9-6dda-06ba85ad8471@arm.com \
    --to=julien.grall@arm.com \
    --cc=andre.przywara@arm.com \
    --cc=shankerd@codeaurora.org \
    --cc=sstabellini@kernel.org \
    --cc=vijay.kilari@gmail.com \
    --cc=xen-devel@lists.xenproject.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.