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[187.189.51.144]) by smtp.gmail.com with ESMTPSA id v123sm1811888oie.20.2020.12.11.06.08.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 11 Dec 2020 06:08:40 -0800 (PST) Subject: Re: [PATCH 1/2] target/arm: add support for FEAT_DIT, Data Independent Timing To: Rebecca Cran , qemu-devel@nongnu.org References: <20201211051359.3231-1-rebecca@nuviainc.com> <20201211051359.3231-2-rebecca@nuviainc.com> From: Richard Henderson Message-ID: <6dd32a22-e3a6-db57-fc5b-9a3da4e1a709@linaro.org> Date: Fri, 11 Dec 2020 08:08:37 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <20201211051359.3231-2-rebecca@nuviainc.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::244; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x244.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 12/10/20 11:13 PM, Rebecca Cran wrote: > Add support for FEAT_DIT. DIT (Data Independent Timing) is a required > feature for ARMv8.4. Since virtual machine execution is largely > nondeterministic, it's implemented as a NOP. Alternately, or additionally, TCG is outside of the security domain (only hardware accelerators like KVM are inside), and so we may implement this as a NOP. > > Signed-off-by: Rebecca Cran > --- > target/arm/cpu.h | 20 +++++++++++++- > target/arm/helper.c | 28 +++++++++++++++++++- > target/arm/internals.h | 6 +++++ > target/arm/translate-a64.c | 14 ++++++++++ > 4 files changed, 66 insertions(+), 2 deletions(-) > > diff --git a/target/arm/cpu.h b/target/arm/cpu.h > index 4c9cbfbd9975..862be662cef7 100644 > --- a/target/arm/cpu.h > +++ b/target/arm/cpu.h > @@ -269,6 +269,7 @@ typedef struct CPUARMState { > uint32_t NF; /* N is bit 31. All other bits are undefined. */ > uint32_t ZF; /* Z set if zero. */ > uint32_t QF; /* 0 or 1 */ > + uint32_t DIT; /* 0 or 1 */ You don't need to add this. Leave the DIT bit in uncached_cpsr. > +++ b/target/arm/translate-a64.c > @@ -1696,6 +1696,20 @@ static void handle_msr_i(DisasContext *s, uint32_t insn, > tcg_temp_free_i32(t1); > break; > > + case 0x1a: /* DIT */ > + if (!dc_isar_feature(aa64_dit, s)) { > + goto do_unallocated; > + } > + if (crm & 1) { > + set_pstate_bits(PSTATE_DIT); > + } else { > + clear_pstate_bits(PSTATE_DIT); > + } > + t1 = tcg_const_i32(s->current_el); > + gen_helper_rebuild_hflags_a64(cpu_env, t1); > + tcg_temp_free_i32(t1); > + break; You don't need to rebuild hflags, because the implementation of DIT is a nop. All you need is to record the pstate change. You may wish to add a comment here about that, reminding the reader. r~