From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 0A86EC4361B for ; Tue, 8 Dec 2020 11:43:16 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id A9FA323A33 for ; Tue, 8 Dec 2020 11:43:15 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org A9FA323A33 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=MsxC3wow35se81ooqTcsyheMSjTPqd+/EBjJTJQwyLg=; b=NyfPW3zMxUYMC6GxkGd1VNVyZ pKEENytUfpyLYpwVjNs0xjeCdbiPwMvCmPsghPtKlNSNmg3g9rWNQKHyE0SEIAacw7O5bQkG7dBtz hsDDdwkOaiXG6pAKqS+E6Py5yZZmbOl+UJxEcFGkI2+WoseghReq3v58DIgULd51y6LjIunOR8Y5q k9pFr0ExugTgKxZTt8NgHbWI/DUhKwF28cQN7+mz5EDqmJErhn0T00nV5U/fbHw4E1os7FlLSQRUp AXc65JGGDi4e9wvsS4MIfjiTk7MoYPXCXpJfxajrENRLur09HMJMAkzqGc16hhAM23O8nAceFiO64 ahKgCaq/Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmbNA-0000eQ-SZ; Tue, 08 Dec 2020 11:41:36 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kmbN8-0000e4-9x for linux-arm-kernel@lists.infradead.org; Tue, 08 Dec 2020 11:41:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 908651FB; Tue, 8 Dec 2020 03:41:27 -0800 (PST) Received: from [10.57.21.180] (unknown [10.57.21.180]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9B4DE3F68F; Tue, 8 Dec 2020 03:41:26 -0800 (PST) Subject: Re: [PATCH 1/2] arm64: Support execute-only permissions with Enhanced PAN To: Catalin Marinas References: <20201119133953.15585-1-vladimir.murzin@arm.com> <20201119133953.15585-2-vladimir.murzin@arm.com> <20201202182303.GC21091@gaia> From: Vladimir Murzin Message-ID: <6de8d380-be38-f6c3-a05f-7daf908eb6de@arm.com> Date: Tue, 8 Dec 2020 11:41:44 +0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 MIME-Version: 1.0 In-Reply-To: <20201202182303.GC21091@gaia> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201208_064134_428430_7EF25C0A X-CRM114-Status: GOOD ( 16.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: keescook@chromium.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 12/2/20 6:23 PM, Catalin Marinas wrote: > On Thu, Nov 19, 2020 at 01:39:52PM +0000, Vladimir Murzin wrote: >> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h >> index 174817b..19147b6 100644 >> --- a/arch/arm64/include/asm/sysreg.h >> +++ b/arch/arm64/include/asm/sysreg.h >> @@ -579,6 +579,7 @@ >> #endif >> >> /* SCTLR_EL1 specific flags. */ >> +#define SCTLR_EL1_EPAN (BIT(57)) >> #define SCTLR_EL1_ATA0 (BIT(42)) >> >> #define SCTLR_EL1_TCF0_SHIFT 38 >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c >> index dcc165b..540245c 100644 >> --- a/arch/arm64/kernel/cpufeature.c >> +++ b/arch/arm64/kernel/cpufeature.c >> @@ -1602,6 +1602,14 @@ static void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused) >> } >> #endif /* CONFIG_ARM64_PAN */ >> >> +#ifdef CONFIG_ARM64_EPAN >> +static void cpu_enable_epan(const struct arm64_cpu_capabilities *__unused) >> +{ >> + sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_EPAN); >> + local_flush_tlb_all(); >> +} >> +#endif /* CONFIG_ARM64_EPAN */ > > Thinking about this, can we not set the SCTLR_EL1.EPAN bit in proc.S > directly, regardless of whether the system supports it or not (it should > be write-ignored)? It would go in INIT_SCTLR_EL1_MMU_ON. We use the > cpufeature entry only for detection, not enabling. > I'll try to restructure that way. Cheers Vladimir _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel