From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D8103C433EF for ; Tue, 5 Apr 2022 09:28:11 +0000 (UTC) Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 2820C83AEF; Tue, 5 Apr 2022 11:28:09 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1649150889; bh=UltAtffEvbu2Si1g31E0Y+SRSfVwVp0yJqdOOU0bkRc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=lKXDxGyMdCwdYl2dI7AO8BoemiceA9Sd6UtWGs8F+dgFuvi3pbhO4KVEAfSDkgsEY d1JGRvnIrpCtgK7n+E1xEW9j558Kq8hBZabzeO0yqBclWNMMTbN5i6GVy56B7TtxI5 Tg+BsUa1Z9NYswIUBFbrOUWUUu7NdHmml9Koz7xSotSphzAZcPmuBlUItBO+AzcYlN mzC+eYavfGrZ+8rRx4OAw6IRzou6ZVGLXcor6oYpViqSVIFaDljgeV3zP/KdxNpHAy U/dGEiK4PgIXY+66LcmByHUhMdCH/i8HJefWJLOeUV87y6c4L/xmKV2xl35Dy5Orou 1S44WBusyZT9w== Received: from [127.0.0.1] (p578adb1c.dip0.t-ipconnect.de [87.138.219.28]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: marex@denx.de) by phobos.denx.de (Postfix) with ESMTPSA id 8877D80291; Tue, 5 Apr 2022 11:28:05 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1649150885; bh=UltAtffEvbu2Si1g31E0Y+SRSfVwVp0yJqdOOU0bkRc=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=wMcFCDcAN1TW2Q2kW62joPyOYmqT1zrKlsh5QR+DB1EjQ5j8XkKaKPTEpD9RzFOMN cC7NiBqZ0CUNtaE2dlMkEuseDTRwMG0kihk4bidWUiWsUbY+B6iL6ijeM3m0qPkVV8 r6ZqyD9ERha2G/0IYqnaI3cWp9yyiUcHNhHV/CEfxMI/W6MlHBBKLuOWuM/893vKpz 0MBbhZ7TeIPb1QOfXY1HlHcJe3fqoVebH1oOJ7tyDSSqc0nsj0H9qrrmE4KRkahYyt iuIwtiW07FdgB4KC/EQTFcPkq8Nf4Y7kdi9OtyGAE9TFA0SABCB4otBBVbbxDm662b Tw9uaOdMTUklQ== Message-ID: <74964c04-b580-366b-fd41-01cb4166eaca@denx.de> Date: Tue, 5 Apr 2022 11:28:05 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.7.0 Subject: Re: [RFC PATCH 2/3] mx6: ddr: Wait before issuing the first MRS cmd Content-Language: en-US To: Francesco Dolcini Cc: Stefano Babic , Fabio Estevam , uboot-imx@nxp.com, Tim Harvey , u-boot@lists.denx.de References: <20220404085119.97792-1-francesco.dolcini@toradex.com> <20220404085119.97792-3-francesco.dolcini@toradex.com> <4fb6e3dd-7c46-43f6-3943-01397e8492a9@denx.de> <20220404145332.GA114170@francesco-nb.int.toradex.com> <07f3d911-fe98-9fcd-d34d-07cee18b48b3@denx.de> <20220405090945.GA18393@francesco-nb.int.toradex.com> From: Marek Vasut In-Reply-To: <20220405090945.GA18393@francesco-nb.int.toradex.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.39 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.5 at phobos.denx.de X-Virus-Status: Clean On 4/5/22 11:09, Francesco Dolcini wrote: > On Mon, Apr 04, 2022 at 09:56:50PM +0200, Marek Vasut wrote: >> On 4/4/22 16:53, Francesco Dolcini wrote: >>> On Mon, Apr 04, 2022 at 03:39:35PM +0200, Marek Vasut wrote: >>>>> --- a/arch/arm/mach-imx/mx6/ddr.c >>>>> +++ b/arch/arm/mach-imx/mx6/ddr.c >>>>> @@ -1526,6 +1526,8 @@ void mx6_ddr3_cfg(const struct mx6_ddr_sysinfo *sysinfo, >>>>> ((sysinfo->ncs == 2) ? 1 : 0) << 30; /* SDE_1 for CS1 */ >>>>> /* Step 8: Write Mode Registers to Init DDR3 devices */ >>>>> + mdelay(1); /* Wait before issuing the first MRS command >>>>> + (tXPR / 500us CKE delay after reset deassertion) */ >>>> >>>> Should we infer this delay from tXPR instead ? >>> >>> I could just delay(tXPR + 500us) and do the exact worst case delay. >>> >>> However I wonder if it is worth doing it, the 1ms delay works in >>> practice, it is big enough to be correct in any case, but small enough >>> not to be a concern on the boot time. >>> >>> Please note that I do not know which timing is violated here >>> (tXPR, the 500us after reset de-assertion or both of them). >> >> Can the tXPR ever be larger than 500us ? > > No, it can't. Max value for 8GB density is 360ns, min value 120ns > for 1GB density (see JEDEC standard, but also mx6/ddr.c). > > Would be fine for you to improve the commit message and code comment > to make this discussion we just had transparent, while keeping the 1ms > delay? Yeah, 1ms is fine. If you do V2, add my: Reviewed-by: Marek Vasut