Re: [v6 0/1] Introduce support for PSF control.

["Saripalli, RK" <rsaripal@amd.com>]

On 5/17/2021 5:00 PM, Ramakrishna Saripalli wrote:
> From: Ramakrishna Saripalli <rk.saripalli@amd.com>
> 
> Predictive Store Forwarding:
> AMD Zen3 processors feature a new technology called
> Predictive Store Forwarding (PSF).
> 
> https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf
> 
> PSF is a hardware-based micro-architectural optimization designed
> to improve the performance of code execution by predicting address
> dependencies between loads and stores.
> 
> How PSF works:
> 
> It is very common for a CPU to execute a load instruction to an address
> that was recently written by a store. Modern CPUs implement a technique
> known as Store-To-Load-Forwarding (STLF) to improve performance in such
> cases. With STLF, data from the store is forwarded directly to the load
> without having to wait for it to be written to memory. In a typical CPU,
> STLF occurs after the address of both the load and store are calculated
> and determined to match.
> 
> PSF expands on this by speculating on the relationship between loads and
> stores without waiting for the address calculation to complete. With PSF,
> the CPU learns over time the relationship between loads and stores.
> If STLF typically occurs between a particular store and load, the CPU will
> remember this.
> 
> In typical code, PSF provides a performance benefit by speculating on
> the load result and allowing later instructions to begin execution
> sooner than they otherwise would be able to.
> 
> Causes of Incorrect PSF:
> 
> Incorrect PSF predictions can occur due to two reasons.
> 
> First, it is possible that the store/load pair had a dependency for a
> while but later stops having a dependency.  This can occur if the address
> of either the store or load changes during the execution of the program.
> 
> The second source of incorrect PSF predictions can occur if there is an
> alias in the PSF predictor structure.  The PSF predictor tracks
> store-load pairs based on portions of their RIP. It is possible that a
> store-load pair which does have a dependency may alias in the predictor
> with another store-load pair which does not.
> 
> This can result in incorrect speculation when the second store/load pair
> is executed.
> 
> Security Analysis:
> 
> Previous research has shown that when CPUs speculate on non-architectural
> paths it can lead to the potential of side channel attacks.
> In particular, programs that implement isolation, also known as
> ‘sandboxing’, entirely in software may need to be concerned with incorrect
> CPU speculation as they can occur due to bad PSF predictions.
> 
> Because PSF speculation is limited to the current program context,
> the impact of bad PSF speculation is very similar to that of
> Speculative Store Bypass (Spectre v4)
> 
> Predictive Store Forwarding controls:
> There are two hardware control bits which influence the PSF feature:
> - MSR 48h bit 2 – Speculative Store Bypass (SSBD)
> - MSR 48h bit 7 – Predictive Store Forwarding Disable (PSFD)
> 
> The PSF feature is disabled if either of these bits are set.  These bits
> are controllable on a per-thread basis in an SMT system. By default, both
> SSBD and PSFD are 0 meaning that the speculation features are enabled.
> 
> While the SSBD bit disables PSF and speculative store bypass, PSFD only
> disables PSF.
> 
> PSFD may be desirable for software which is concerned with the
> speculative behavior of PSF but desires a smaller performance impact than
> setting SSBD.
> 
> Support for PSFD is indicated in CPUID Fn8000_0008 EBX[28].
> All processors that support PSF will also support PSFD.
> 
> ChangeLogs:
>     V6->V5:
>     	  Moved PSF control code to arch/x86/kernel/cpu/bugs.c
>     	      PSF mitigation is similar to spec_control_bypass mitigation.
>     	  PSF mitigation has only ON and OFF controls.
>     	  Kernel parameter changed to predictive_store_fwd_disable.
>     V5->V4:
>           Replaced rdmsrl and wrmsrl for setting SPEC_CTRL_PSFD with 
>              a single call to msr_set_bit.
>           Removed temporary variable to read and write the MSR
>     V4->V3:
>      	  Write to MSR_IA32_SPEC_CTRL properly
>      	     Read MSR, modify PSFD bit based on kernel parameter and
>      	     write back to MSR.
>      	     
> 	     Changes made in psf_cmdline() and check_bugs().
>     V3->V2:
>           Set the X86_FEATURE_SPEC_CTRL_MSR cap in boot cpu caps.
>           Fix kernel documentation for the kernel parameter.
>           Rename PSF to a control instead of mitigation.
> 
>     V1->V2:
>         - Smashed multiple commits into one commit.
>         - Rename PSF to a control instead of mitigation.
> 
>     V1:
>         - Initial patchset.
>         - Kernel parameter controls enable and disable of PSF.
> 
> 
> 

Gentle ping. Any more concerns or feedback with this patch series?.
Thanks,
RK
> 
> Ramakrishna Saripalli (1):
>   x86/bugs: Implement mitigation for Predictive Store Forwarding
> 
>  .../admin-guide/kernel-parameters.txt         |  5 +
>  arch/x86/include/asm/cpufeatures.h            |  1 +
>  arch/x86/include/asm/msr-index.h              |  2 +
>  arch/x86/include/asm/nospec-branch.h          |  6 ++
>  arch/x86/kernel/cpu/bugs.c                    | 94 +++++++++++++++++++
>  5 files changed, 108 insertions(+)
> 
> 
> base-commit: 0e16f466004d7f04296b9676a712a32a12367d1f
>