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Fri, 03 Dec 2021 12:53:57 +0000 Date: Fri, 03 Dec 2021 12:53:56 +0000 Message-ID: <874k7pn923.wl-maz@kernel.org> From: Marc Zyngier To: Ard Biesheuvel Cc: linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk, Nicolas Pitre , Arnd Bergmann , Kees Cook , Keith Packard , Linus Walleij , Nick Desaulniers , Tony Lindgren , Vladimir Murzin , Jesse Taube Subject: Re: [PATCH v3 00/14] ARM: enable IRQ stacks and vmap'ed stacks for UP In-Reply-To: <20211203100903.334206-1-ardb@kernel.org> References: <20211203100903.334206-1-ardb@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ardb@kernel.org, linux-arm-kernel@lists.infradead.org, linux@armlinux.org.uk, nico@fluxnic.net, arnd@arndb.de, keescook@chromium.org, keithpac@amazon.com, linus.walleij@linaro.org, ndesaulniers@google.com, tony@atomide.com, vladimir.murzin@arm.com, mr.bossman075@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211203_045402_373043_A3ACDC7C X-CRM114-Status: GOOD ( 26.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 03 Dec 2021 10:08:49 +0000, Ard Biesheuvel wrote: > > First, enable the use of the TLS register to hold the 'current' pointer > for all configurations that can support it, including non-SMP ones that > target v6k or later CPUs, and multi-platform SMP ones that also support > v6 based UP systems. > > The remaining configurations are all strictly UP, which means we can > switch to a global variable to hold the current pointer. By doing this, > we can enable THREAD_INFO_IN_TASK, which moves thread info off the > stack, protecting it from overflows. It also permits us to enable IRQ > stacks and vmap'ed stacks for UP configurations as well. > > Supporting v6 cores without SMP extensions in SMP configurations (e.g., > omap2plus_defconfig or imx_v6_v7_defconfig) makes this a bit tricky, and > this is a feature we may consider dropping entirely in the future. But > for the time being, we can support this mode as well. > > The accesses to the global variable holding 'current' are constructed in > a way that ensures that no literal pool accesses (and associated D-cache > misses) are needed unless the access is from a module and module PLTs > are enabled. This means that accessing 'current' is just as costly as > before, as it used to require some arithmetic involving the stack > pointer and a load from the thread_info::task field. > > However, accessing thread_info itself now also involves a load, although > it should be noted that all thread_info and current accesses now go via > the same variable, which is therefore expected to be hot in the caches > at all times. FWIW, I've given this a go on a Netwinder (of the Footbridge family), and nothing caught fire. I'm not using modules though. Tested-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel