All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jani Nikula <jani.nikula@linux.intel.com>
To: Rodrigo Vivi <rodrigo.vivi@intel.com>,
	vathsala nagaraju <vathsala.nagaraju@intel.com>
Cc: Puthikorn Voravootivat <puthik@chromium.org>,
	intel-gfx@lists.freedesktop.org,
	Maulik V Vaghela <maulik.v.vaghela@intel.com>
Subject: Re: [PATCH] drm/i915/psr: vbt change for psr
Date: Mon, 09 Apr 2018 16:57:04 +0300	[thread overview]
Message-ID: <87h8okjxe7.fsf@intel.com> (raw)
In-Reply-To: <20180406174123.GB8964@intel.com>

On Fri, 06 Apr 2018, Rodrigo Vivi <rodrigo.vivi@intel.com> wrote:
> On Fri, Apr 06, 2018 at 10:58:51PM +0530, vathsala nagaraju wrote:
>> From: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> 
>> For psr block #9, the vbt description has moved to options [0-3] for
>> TP1,TP2,TP3 Wakeup time from decimal value without any change to vbt
>> structure. Since spec does not  mention from which VBT version this
>> change was added to vbt.bsf file, we cannot depend on bdb->version check
>> to change for all the platforms.
>> 
>> There is RCR inplace for GOP team to  provide the version number
>> to make generic change. Since Kabylake with bdb version 209 is having this
>> change, limiting this change to kbl and version 209+ to unblock google.
>> 
>> bspec 20131
>> 
>> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
>> CC: Puthikorn Voravootivat <puthik@chromium.org>
>> 
>> Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
>> Signed-off-by: Vathsala Nagaraju <vathsala.nagaraju@intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h   |  1 +
>>  drivers/gpu/drm/i915/intel_bios.c |  2 +-
>>  drivers/gpu/drm/i915/intel_psr.c  | 84 ++++++++++++++++++++++++++-------------
>>  3 files changed, 59 insertions(+), 28 deletions(-)
>> 
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
>> index 5373b17..a47be19b 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -1075,6 +1075,7 @@ struct intel_vbt_data {
>>  		enum psr_lines_to_wait lines_to_wait;
>>  		int tp1_wakeup_time;
>>  		int tp2_tp3_wakeup_time;
>> +		int bdb_version;
>
> please keep the vbt stuff inside intel_bios.c
>
> so there at intel_bios.c you parse the vbt and based on the vbt version
> you export in a standard way to intel_psr.c

Exactly! struct intel_vbt_data is supposed to be an abstraction.

BR,
Jani.

>
>>  	} psr;
>>  
>>  	struct {
>> diff --git a/drivers/gpu/drm/i915/intel_bios.c b/drivers/gpu/drm/i915/intel_bios.c
>> index c5c7530..cfefd32 100644
>> --- a/drivers/gpu/drm/i915/intel_bios.c
>> +++ b/drivers/gpu/drm/i915/intel_bios.c
>> @@ -658,7 +658,7 @@ static int intel_bios_ssc_frequency(struct drm_i915_private *dev_priv,
>>  		DRM_DEBUG_KMS("No PSR BDB found.\n");
>>  		return;
>>  	}
>> -
>> +	dev_priv->vbt.psr.bdb_version = bdb->version;
>>  	psr_table = &psr->psr_table[panel_type];
>>  
>>  	dev_priv->vbt.psr.full_link = psr_table->full_link;
>> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
>> index 2d53f73..e470d5e 100644
>> --- a/drivers/gpu/drm/i915/intel_psr.c
>> +++ b/drivers/gpu/drm/i915/intel_psr.c
>> @@ -353,24 +353,45 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>>  	if (dev_priv->psr.link_standby)
>>  		val |= EDP_PSR_LINK_STANDBY;
>>  
>> -	if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> -		val |= EDP_PSR_TP1_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> -		val |= EDP_PSR_TP1_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> -		val |= EDP_PSR_TP1_TIME_100us;
>> -	else
>> -		val |= EDP_PSR_TP1_TIME_0us;
>> -
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR_TP2_TP3_TIME_500us;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR_TP2_TP3_TIME_100us;
>> -	else
>> -		val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +		if (dev_priv->vbt.psr.tp1_wakeup_time == 0)
>> +			val |= EDP_PSR_TP1_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 1)
>> +			val |= EDP_PSR_TP1_TIME_100us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time == 2)
>> +			val |= EDP_PSR_TP1_TIME_2500us;
>> +		else
>> +			val |= EDP_PSR_TP1_TIME_0us;
>> +	} else {
>> +		if (dev_priv->vbt.psr.tp1_wakeup_time > 5)
>> +			val |= EDP_PSR_TP1_TIME_2500us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 1)
>> +			val |= EDP_PSR_TP1_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp1_wakeup_time > 0)
>> +			val |= EDP_PSR_TP1_TIME_100us;
>> +		else
>> +			val |= EDP_PSR_TP1_TIME_0us;
>> +	}
>>  
>> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>> +			val |=  EDP_PSR_TP2_TP3_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> +		else
>> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +	} else {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> +			val |= EDP_PSR_TP2_TP3_TIME_2500us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> +			val |= EDP_PSR_TP2_TP3_TIME_500us;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +			val |= EDP_PSR_TP2_TP3_TIME_100us;
>> +		else
>> +			val |= EDP_PSR_TP2_TP3_TIME_0us;
>> +	}
>>  	if (intel_dp_source_supports_hbr2(intel_dp) &&
>>  	    drm_dp_tps3_supported(intel_dp->dpcd))
>>  		val |= EDP_PSR_TP1_TP3_SEL;
>> @@ -405,16 +426,25 @@ static void hsw_activate_psr2(struct intel_dp *intel_dp)
>>  	}
>>  
>>  	val |= EDP_PSR2_FRAME_BEFORE_SU(dev_priv->psr.sink_sync_latency + 1);
>> -
>> -	if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> -		val |= EDP_PSR2_TP2_TIME_2500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> -		val |= EDP_PSR2_TP2_TIME_500;
>> -	else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> -		val |= EDP_PSR2_TP2_TIME_100;
>> -	else
>> -		val |= EDP_PSR2_TP2_TIME_50;
>> -
>> +	if (dev_priv->vbt.psr.bdb_version >= 209 && IS_KABYLAKE(dev_priv)) {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 0)
>> +			val |= EDP_PSR2_TP2_TIME_500;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 1)
>> +			val |= EDP_PSR2_TP2_TIME_100;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time == 2)
>> +			val |= EDP_PSR2_TP2_TIME_2500;
>> +		else
>> +			val |= EDP_PSR2_TP2_TIME_50;
>> +	} else {
>> +		if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 5)
>> +			val |= EDP_PSR2_TP2_TIME_2500;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 1)
>> +			val |= EDP_PSR2_TP2_TIME_500;
>> +		else if (dev_priv->vbt.psr.tp2_tp3_wakeup_time > 0)
>> +			val |= EDP_PSR2_TP2_TIME_100;
>> +		else
>> +			val |= EDP_PSR2_TP2_TIME_50;
>> +	}
>>  	I915_WRITE(EDP_PSR2_CTL, val);
>>  }
>>  
>> -- 
>> 1.9.1
>> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Jani Nikula, Intel Open Source Technology Center
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2018-04-09 13:56 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-06 17:28 [PATCH] drm/i915/psr: vbt change for psr vathsala nagaraju
2018-04-06 17:41 ` Rodrigo Vivi
2018-04-09 13:57   ` Jani Nikula [this message]
2018-04-06 18:01 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-04-06 21:55 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-04-11 17:57 [PATCH] " vathsala nagaraju
2018-04-12  9:26 ` Jani Nikula
2018-04-19  7:42 vathsala nagaraju
2018-04-19 13:35 ` Jani Nikula
2018-04-20  6:30   ` vathsala nagaraju
2018-04-27  7:52     ` Jani Nikula
2018-05-02  9:13 vathsala nagaraju
2018-05-02 21:15 ` Rodrigo Vivi
2018-05-03  3:21   ` vathsala nagaraju
2018-05-03  6:59   ` Jani Nikula
2018-05-03  7:07 ` Jani Nikula
2018-05-03  9:08 vathsala nagaraju
2018-05-03  9:39 ` Jani Nikula
2018-05-03 11:36 vathsala nagaraju
2018-05-03 15:44 ` Rodrigo Vivi
2018-05-03 17:13   ` Nagaraju, Vathsala
2018-05-04 23:13     ` Puthikorn Voravootivat
2018-05-14  3:32 vathsala nagaraju
2018-05-15 22:55 ` Puthikorn Voravootivat
2018-05-16  3:48   ` vathsala nagaraju
2018-05-15 23:03 ` Dhinakaran Pandiyan
2018-05-16  3:44   ` vathsala nagaraju
2018-05-16  8:08     ` Jani Nikula
2018-05-16 17:44       ` Dhinakaran Pandiyan
2018-05-17  8:02         ` Jani Nikula
2018-05-17 20:12           ` Dhinakaran Pandiyan
2018-05-16  8:13     ` Jani Nikula
2018-05-16 22:04     ` Dhinakaran Pandiyan
2018-05-18  8:55 vathsala nagaraju
2018-05-18  9:31 ` Jani Nikula
2018-05-22  4:48   ` Nagaraju, Vathsala
2018-05-22  8:05     ` Jani Nikula
2018-05-22  8:36       ` Nagaraju, Vathsala
2018-05-22  9:27 vathsala nagaraju
2018-05-22 12:46 ` Jani Nikula
2018-05-24 13:04   ` Jani Nikula
2018-05-23  3:05 vathsala nagaraju
2018-05-23 10:03 ` Jani Nikula
2018-05-23 12:55   ` Nagaraju, Vathsala
2018-05-23 13:10     ` Jani Nikula

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=87h8okjxe7.fsf@intel.com \
    --to=jani.nikula@linux.intel.com \
    --cc=intel-gfx@lists.freedesktop.org \
    --cc=maulik.v.vaghela@intel.com \
    --cc=puthik@chromium.org \
    --cc=rodrigo.vivi@intel.com \
    --cc=vathsala.nagaraju@intel.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.