From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26B54C48BE5 for ; Tue, 15 Jun 2021 15:20:13 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 02B0B6115C for ; Tue, 15 Jun 2021 15:20:12 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231466AbhFOPWP (ORCPT ); Tue, 15 Jun 2021 11:22:15 -0400 Received: from foss.arm.com ([217.140.110.172]:38200 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230462AbhFOPWL (ORCPT ); Tue, 15 Jun 2021 11:22:11 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A440D6E; Tue, 15 Jun 2021 08:20:06 -0700 (PDT) Received: from e113632-lin (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A155D3F70D; Tue, 15 Jun 2021 08:20:05 -0700 (PDT) From: Valentin Schneider To: Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: Re: [RFC PATCH v2 09/10] irqchip/gic: Convert to handle_strict_flow_irq() In-Reply-To: <87pmx5g9ud.mognet@arm.com> References: <20210525173255.620606-1-valentin.schneider@arm.com> <20210525173255.620606-10-valentin.schneider@arm.com> <87wnrks6y5.wl-maz@kernel.org> <87pmx5g9ud.mognet@arm.com> Date: Tue, 15 Jun 2021 16:20:03 +0100 Message-ID: <87lf7bb1ek.mognet@arm.com> MIME-Version: 1.0 Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/06/21 11:25, Valentin Schneider wrote: > On 27/05/21 13:21, Marc Zyngier wrote: >> On Tue, 25 May 2021 18:32:54 +0100, >> Valentin Schneider wrote: >>> @@ -1116,8 +1116,16 @@ static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, >>> >>> if (use_eoimode1) { >>> gic->chip.irq_mask = gic_eoimode1_mask_irq; >>> + gic->chip.irq_ack = gic_eoi_irq; >>> gic->chip.irq_eoi = gic_eoimode1_eoi_irq; >>> gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; >>> + >>> + /* >>> + * eoimode0 shouldn't expose FLOW_MASK because the priority >>> + * drop is undissociable from the deactivation, and we do need >>> + * the priority drop to happen within the flow handler. >>> + */ >>> + gic->chip.flags |= IRQCHIP_AUTOMASKS_FLOW | IRQCHIP_EOI_THREADED; >>> } >>> >>> if (gic == &gic_data[0]) { >> >> How about GICv2M, GICv3-MBI, and the collection of widget that build a >> domain on top of a GIC domain? I'm worried that they now all need >> updating one way or another... >> > > Hmph, that's a good point. It's been a while since I've last stared at the > v2m, I'll go try to page that back in. > It's taken me a while to get back to this, apologies. Here's where I'm at: At the very least these need the +.irq_ack() treatment, same as the ITS chips. We can get around this by giving msi_domain_update_chip_ops() some invoke-first-non-NULL default callbacks, as you've suggested in: http://lore.kernel.org/r/87y2c0s748.wl-maz@kernel.org Now, looking at this made me think about which irq_chip flags are being used where, and, well... PCI-MSI IRQs are deemed 'oneshot safe', but platform-MSI ones aren't. So for instance, if a GICv2M pMSI IRQ gets force-threaded, we'll make it IRQS_ONESHOT. However, this is still just a glorified SPI as all mask, ack and eoi operations will be the root chip's, so we should be able to apply the eoimode=1 automask trickery to it. This won't happen with the current patches, since the ->chip we'll seeing in handle_strict_flow_irq() will be gicv2m_pmsi_irq_chip. We *could* give that one the required flags, but what actually matters for the automask thing are the flags of first chip in the hiearachy that has "proper" ack+eoi callbacks. I don't see a nice way of handling this right now... >> M. >> >> -- >> Without deviation from the norm, progress is not possible. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.9 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id B82D3C48BE5 for ; Tue, 15 Jun 2021 19:43:42 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6BE7B61166 for ; Tue, 15 Jun 2021 19:43:42 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6BE7B61166 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:MIME-Version:Message-ID:Date:References :In-Reply-To:Subject:Cc:To:From:Reply-To:Content-ID:Content-Description: Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID: List-Owner; bh=7NyLo89rtRhiGucJKEI4MhRCYd5bb2AIR918Ykr+mMU=; b=wcdG6EmVzrgHJB BYsr71kXLZsZEM0ddRQy5KEG5fwtMgOiX7MutSJxHvgbearHHznzwabcR7RGJdSXvvWA2lKAty3m6 OURIMv9cerxEKBGHzF315dMjop211FzwwTtJUqEXvSmNySLtuqRHXNoMgAKCIHDdKHYd9FzJYJjO2 bX+ObfXTuVgNARIfzX0Da8loHgOz3MECSgEg4m3yGDvGcisZng3YmaNj/feX4QjTLuw6jb2lEQZhG 40CUA8MeVgEBxzhUYr820PJW+lqAiLRHgXHj40dtqLZ/MzLHrKiBVTYDBm4apzfylvoJkZ76OJ/d/ 7RMx9waCR/jee0MAJlxg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ltEwd-002X7b-8X; Tue, 15 Jun 2021 19:41:55 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1ltArJ-000ut0-0g for linux-arm-kernel@lists.infradead.org; Tue, 15 Jun 2021 15:20:10 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 8A440D6E; Tue, 15 Jun 2021 08:20:06 -0700 (PDT) Received: from e113632-lin (usa-sjc-imap-foss1.foss.arm.com [10.121.207.14]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A155D3F70D; Tue, 15 Jun 2021 08:20:05 -0700 (PDT) From: Valentin Schneider To: Marc Zyngier Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Thomas Gleixner , Lorenzo Pieralisi , Vincenzo Frascino Subject: Re: [RFC PATCH v2 09/10] irqchip/gic: Convert to handle_strict_flow_irq() In-Reply-To: <87pmx5g9ud.mognet@arm.com> References: <20210525173255.620606-1-valentin.schneider@arm.com> <20210525173255.620606-10-valentin.schneider@arm.com> <87wnrks6y5.wl-maz@kernel.org> <87pmx5g9ud.mognet@arm.com> Date: Tue, 15 Jun 2021 16:20:03 +0100 Message-ID: <87lf7bb1ek.mognet@arm.com> MIME-Version: 1.0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210615_082009_183162_42CD6F23 X-CRM114-Status: GOOD ( 19.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 01/06/21 11:25, Valentin Schneider wrote: > On 27/05/21 13:21, Marc Zyngier wrote: >> On Tue, 25 May 2021 18:32:54 +0100, >> Valentin Schneider wrote: >>> @@ -1116,8 +1116,16 @@ static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, >>> >>> if (use_eoimode1) { >>> gic->chip.irq_mask = gic_eoimode1_mask_irq; >>> + gic->chip.irq_ack = gic_eoi_irq; >>> gic->chip.irq_eoi = gic_eoimode1_eoi_irq; >>> gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; >>> + >>> + /* >>> + * eoimode0 shouldn't expose FLOW_MASK because the priority >>> + * drop is undissociable from the deactivation, and we do need >>> + * the priority drop to happen within the flow handler. >>> + */ >>> + gic->chip.flags |= IRQCHIP_AUTOMASKS_FLOW | IRQCHIP_EOI_THREADED; >>> } >>> >>> if (gic == &gic_data[0]) { >> >> How about GICv2M, GICv3-MBI, and the collection of widget that build a >> domain on top of a GIC domain? I'm worried that they now all need >> updating one way or another... >> > > Hmph, that's a good point. It's been a while since I've last stared at the > v2m, I'll go try to page that back in. > It's taken me a while to get back to this, apologies. Here's where I'm at: At the very least these need the +.irq_ack() treatment, same as the ITS chips. We can get around this by giving msi_domain_update_chip_ops() some invoke-first-non-NULL default callbacks, as you've suggested in: http://lore.kernel.org/r/87y2c0s748.wl-maz@kernel.org Now, looking at this made me think about which irq_chip flags are being used where, and, well... PCI-MSI IRQs are deemed 'oneshot safe', but platform-MSI ones aren't. So for instance, if a GICv2M pMSI IRQ gets force-threaded, we'll make it IRQS_ONESHOT. However, this is still just a glorified SPI as all mask, ack and eoi operations will be the root chip's, so we should be able to apply the eoimode=1 automask trickery to it. This won't happen with the current patches, since the ->chip we'll seeing in handle_strict_flow_irq() will be gicv2m_pmsi_irq_chip. We *could* give that one the required flags, but what actually matters for the automask thing are the flags of first chip in the hiearachy that has "proper" ack+eoi callbacks. I don't see a nice way of handling this right now... >> M. >> >> -- >> Without deviation from the norm, progress is not possible. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel