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References: <20181123144558.5048-1-richard.henderson@linaro.org>
	<20181123144558.5048-11-richard.henderson@linaro.org>
From: Alex =?utf-8?Q?Benn=C3=A9e?= <alex.bennee@linaro.org>
In-reply-to: <20181123144558.5048-11-richard.henderson@linaro.org>
Date: Fri, 30 Nov 2018 17:25:46 +0000
Message-ID: <87r2f232at.fsf@linaro.org>
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Subject: Re: [Qemu-devel] [PATCH for-4.0 v2 10/37] tcg/aarch64: Add
 constraints for x0, x1, x2
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To: qemu-devel@nongnu.org
Cc: Alistair.Francis@wdc.com


Richard Henderson <richard.henderson@linaro.org> writes:

> These are function call arguments that we will need soon.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>

> ---
>  tcg/aarch64/tcg-target.inc.c | 12 ++++++++++++
>  1 file changed, 12 insertions(+)
>
> diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c
> index 30091f6a69..148de0b7f2 100644
> --- a/tcg/aarch64/tcg-target.inc.c
> +++ b/tcg/aarch64/tcg-target.inc.c
> @@ -125,6 +125,18 @@ static const char *target_parse_constraint(TCGArgCon=
straint *ct,
>                                             const char *ct_str, TCGType t=
ype)
>  {
>      switch (*ct_str++) {
> +    case 'a': /* x0 */
> +        ct->ct |=3D TCG_CT_REG;
> +        tcg_regset_set_reg(ct->u.regs, TCG_REG_X0);
> +        break;
> +    case 'b': /* x1 */
> +        ct->ct |=3D TCG_CT_REG;
> +        tcg_regset_set_reg(ct->u.regs, TCG_REG_X1);
> +        break;
> +    case 'c': /* x2 */
> +        ct->ct |=3D TCG_CT_REG;
> +        tcg_regset_set_reg(ct->u.regs, TCG_REG_X2);
> +        break;
>      case 'r': /* general registers */
>          ct->ct |=3D TCG_CT_REG;
>          ct->u.regs |=3D 0xffffffffu;


--
Alex Benn=C3=A9e