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[83.35.25.14]) by smtp.gmail.com with ESMTPSA id l15sm16975530wme.42.2021.09.19.11.22.51 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Sun, 19 Sep 2021 11:22:51 -0700 (PDT) Message-ID: <95b28dff-7a3c-73fa-2449-c41110e12642@amsat.org> Date: Sun, 19 Sep 2021 20:22:50 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.1.0 Subject: Re: [PATCH v2 19/41] hw/core: Add TCGCPUOps.record_sigsegv Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20210918184527.408540-1-richard.henderson@linaro.org> <20210918184527.408540-20-richard.henderson@linaro.org> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: <20210918184527.408540-20-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x334.google.com X-Spam_score_int: 4 X-Spam_score: 0.4 X-Spam_bar: / X-Spam_report: (0.4 / 5.0 requ) DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FORGED_FROMDOMAIN=0.249, FREEMAIL_FROM=0.001, HEADER_FROM_DIFFERENT_DOMAINS=0.25, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent@vivier.eu Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/18/21 20:45, Richard Henderson wrote: > Add a new user-only interface for updating cpu state before > raising a signal. This will replace tlb_fill for user-only > and should result in less boilerplate for each guest. > > Signed-off-by: Richard Henderson > --- > include/hw/core/tcg-cpu-ops.h | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h > index 4a4c4053e3..e229a40772 100644 > --- a/include/hw/core/tcg-cpu-ops.h > +++ b/include/hw/core/tcg-cpu-ops.h > @@ -114,6 +114,32 @@ struct TCGCPUOps { > */ > bool (*io_recompile_replay_branch)(CPUState *cpu, > const TranslationBlock *tb); > +#else > + /** > + * record_sigsegv: > + * @cpu: cpu context > + * @addr: faulting guest address > + * @access_type: access was read/write/execute > + * @maperr: true for invalid page, false for permission fault > + * @ra: host pc for unwinding > + * > + * We are about to raise SIGSEGV with si_code set for @maperr, > + * and si_addr set for @addr. Record anything further needed > + * for the signal ucontext_t. > + * > + * If the emulated kernel does not provide anything to the signal > + * handler with anything besides the user context registers, and > + * the siginfo_t, then this hook need do nothing and may be omitted. > + * Otherwise, record the data and return; the caller will raise > + * the signal, unwind the cpu state, and return to the main loop. > + * > + * If it is simpler to re-use the sysemu tlb_fill code, @ra is provided > + * so that a "normal" cpu exception can be raised. In this case, > + * the signal must be raised by the architecture cpu_loop. > + */ Shouldn't it have the QEMU_NORETURN attribute? > + void (*record_sigsegv)(CPUState *cpu, vaddr addr, > + MMUAccessType access_type, > + bool maperr, uintptr_t ra); > #endif /* CONFIG_SOFTMMU */ > #endif /* NEED_CPU_H */ > >