From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-17.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C72CDC4361B for ; Fri, 18 Dec 2020 14:44:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 8BCDD23AC8 for ; Fri, 18 Dec 2020 14:44:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728002AbgLROoO (ORCPT ); Fri, 18 Dec 2020 09:44:14 -0500 Received: from fllv0015.ext.ti.com ([198.47.19.141]:40594 "EHLO fllv0015.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726903AbgLROoN (ORCPT ); Fri, 18 Dec 2020 09:44:13 -0500 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BIEgJ1h002175; Fri, 18 Dec 2020 08:42:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608302539; bh=pTnSOVQlYaLLFPXX46y4VH9Zff6M5493tQ8KFZNlnPg=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=qVoAcJrFpHv8UTLXJKvQVTwSvNJ8ZEnkeV7DBTCkURzuONJJ6bdsu7HivHuSkK4uZ rCK+HZSjzBIG4mlmB6a+4y+SMxztzzM9J38Oqaf0i/GXQ5uULFPBjYrK63pAiC3ygn lNtfC3xxZpPYoxzBWgqwwMBSjjYLM6IeAMvwXP4k= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BIEgJQ7111684 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Dec 2020 08:42:19 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 18 Dec 2020 08:42:18 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 18 Dec 2020 08:42:18 -0600 Received: from [10.250.235.36] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BIEgEl9113653; Fri, 18 Dec 2020 08:42:15 -0600 Subject: Re: [PATCH v5] PCI: cadence: Retrain Link to work around Gen2 training defect. To: Rob Herring CC: Tom Joseph , Bjorn Helgaas , Nadeem Athani , linux-omap , PCI , linux-arm-kernel , "linux-kernel@vger.kernel.org" , Milind Parab , Swapnil Kashinath Jakhade , Parshuram Raju Thombare References: <20201215070009.27937-1-kishon@ti.com> <1ec78477-dadc-cbef-406f-568f44b6c62d@ti.com> From: Kishon Vijay Abraham I Message-ID: <96ca64cb-ec3a-bb83-2de3-775034ba844b@ti.com> Date: Fri, 18 Dec 2020 20:12:13 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 7bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Rob, On 16/12/20 10:31 pm, Rob Herring wrote: > On Wed, Dec 16, 2020 at 9:01 AM Kishon Vijay Abraham I wrote: >> >> Hi Rob, >> >> On 15/12/20 9:23 pm, Rob Herring wrote: >>> On Tue, Dec 15, 2020 at 1:00 AM Kishon Vijay Abraham I wrote: >>>> >>>> From: Nadeem Athani >>>> >>>> Cadence controller will not initiate autonomous speed change if strapped as >>>> Gen2. The Retrain Link bit is set as quirk to enable this speed change. >>>> >>>> Signed-off-by: Nadeem Athani >>>> [kishon@ti.com: Enable the workaround for TI's J721E SoC] >>>> Signed-off-by: Kishon Vijay Abraham I >>>> --- >>>> Hi Lorenzo, >>>> The previous version of the patch can be found at [1]. >>>> I slightly re-worked the patch from Nadeem >>>> *) Removed additional Link Up Check >>>> *) Removed quirk from pcie-cadence-plat.c >>>> *) Also removed additional compatible >>>> "cdns,cdns-pcie-host-quirk-retrain" added in that series >>>> *) Enabled the quirk for J721E >>>> [1] -> http://lore.kernel.org/r/20201211144236.3825-1-nadeem@cadence.com >>>> >>>> drivers/pci/controller/cadence/pci-j721e.c | 3 + >>>> .../controller/cadence/pcie-cadence-host.c | 67 ++++++++++++++----- >>>> drivers/pci/controller/cadence/pcie-cadence.h | 11 ++- >>>> 3 files changed, 62 insertions(+), 19 deletions(-) >>>> >>>> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c >>>> index dac1ac8a7615..baf729850cb1 100644 >>>> --- a/drivers/pci/controller/cadence/pci-j721e.c >>>> +++ b/drivers/pci/controller/cadence/pci-j721e.c >>>> @@ -64,6 +64,7 @@ enum j721e_pcie_mode { >>>> >>>> struct j721e_pcie_data { >>>> enum j721e_pcie_mode mode; >>>> + bool quirk_retrain_flag; >>>> }; >>>> >>>> static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) >>>> @@ -280,6 +281,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = { >>>> >>>> static const struct j721e_pcie_data j721e_pcie_rc_data = { >>>> .mode = PCI_MODE_RC, >>>> + .quirk_retrain_flag = true, >>>> }; >>>> >>>> static const struct j721e_pcie_data j721e_pcie_ep_data = { >>>> @@ -388,6 +390,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) >>>> >>>> bridge->ops = &cdns_ti_pcie_host_ops; >>>> rc = pci_host_bridge_priv(bridge); >>>> + rc->quirk_retrain_flag = data->quirk_retrain_flag; >>>> >>>> cdns_pcie = &rc->pcie; >>>> cdns_pcie->dev = dev; >>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c >>>> index 811c1cb2e8de..773c0d1137ed 100644 >>>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c >>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c >>>> @@ -77,6 +77,50 @@ static struct pci_ops cdns_pcie_host_ops = { >>>> .write = pci_generic_config_write, >>>> }; >>>> >>>> +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) >>>> +{ >>>> + struct device *dev = pcie->dev; >>>> + int retries; >>>> + >>>> + /* Check if the link is up or not */ >>>> + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { >>>> + if (cdns_pcie_link_up(pcie)) { >>>> + dev_info(dev, "Link up\n"); >>>> + return 0; >>>> + } >>>> + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); >>>> + } >>>> + >>>> + return -ETIMEDOUT; >>>> +} >>>> + >>>> +static void cdns_pcie_retrain(struct cdns_pcie *pcie) >>>> +{ >>>> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; >>>> + u16 lnk_stat, lnk_ctl; >>>> + >>>> + /* >>>> + * Set retrain bit if current speed is 2.5 GB/s, >>>> + * but the PCIe root port support is > 2.5 GB/s. >>> >>> If you don't have the retrain quirk, wouldn't this condition never >>> happen and then the function is just a nop? So this could just be >>> called unconditionally. >> >> Yeah, but only for the quirk we have to retrain to go to GEN2 speed >> mode. Else the HW will automatically retrain and go to GEN2. > > Again, so you don't need a flag for this. Comparing the speed is > enough. IOW, all you need is: > > if (current speed < advertised speed) > do retrain > > The question is the condition ever true and you don't want to do a > retrain? I could see higher speeds being unstable or something, but For all GEN1 cards there will be re-train (since the Cadence IP RC is GEN2 or more say). This is going to be true for older Cadence IPs and newer Cadence IPs (where Cadence has enabled HW re-training). The quirk will prevent SW re-training for newer Cadence IPs when a GEN1 card is connected. > then 'advertised speed' would be lowered in that case (to prevent auto > retraining, right?) and the condition would be false. I don't think the value in PCI_EXP_LNKCAP will change for unstable links. But yeah it'll fall back to GEN1 based on link training and if the link is unstable it'll again fall back to GEN1 on link RE-training. Thanks, Kishon From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,NICE_REPLY_A,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7C54EC4361B for ; Fri, 18 Dec 2020 16:59:51 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0D24123B53 for ; Fri, 18 Dec 2020 16:59:51 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0D24123B53 Authentication-Results: mail.kernel.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=EAasflZpBIx0YpZpu2zvwyPoiiM8B5AkmZkjyOrVqpw=; b=LE+lSChQrQmH/3nR1Vyu9T4GZ iRqYesZcUKvJ+4KDBOoEa0RC11I6DpyotMc3qbm3C/eM1XVV72DWNo1YTLF+GvFDQGn7hc1Qr4A/U dVl1MBMFzFHV1DHiD/TPCO6HxaAbV2ANvrwUHNMzGJjSpjoYBloL78hJkVgh1xIkBOBVcNwanVE5y wMGq1ZDRIirU9YitXBiiTOIONAwmzp5kJshGhHQ6jytGyMVAUSOe04xpg+vNdneZQJrCC6aI2ujw5 t4jdnUZPpiTa6y/i54/nt6IO6JEvOdu3wbrnyUQpv10IYpKK19evH1M7ZEt+PrCpQTSnoUmLzUuTE ugUeK3zSA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kqIzK-0000FW-Mv; Fri, 18 Dec 2020 16:52:23 +0000 Received: from casper.infradead.org ([2001:8b0:10b:1236::1]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kqIy8-000084-KL for linux-arm-kernel@merlin.infradead.org; Fri, 18 Dec 2020 16:51:14 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=casper.20170209; h=Content-Transfer-Encoding:Content-Type: In-Reply-To:MIME-Version:Date:Message-ID:From:References:CC:To:Subject:Sender :Reply-To:Content-ID:Content-Description; bh=pTnSOVQlYaLLFPXX46y4VH9Zff6M5493tQ8KFZNlnPg=; b=jBjleRtjwvn+KsafyM6zwTq2hX EPCpnsBO8En2+DyfFVV46fr/IrUhPiI//6jAKRjRdCEcGR1EGUfrPNJvHFCOX13oVCvyWj1oGbiUW 7/2u7kROwZFaQMCsY82LGEGVY9ukXyzlCJBs+WJ6A3YHdjmeLDKeu+IyZTTjMWMPt6DZtBSf7OSnW RVJ/14DyRP58vs8FUuzAfhgsT6HkdDjIbrlWkeref7qHucMJAA6EC+E/esf/PH6epkG9UXsgNqQv9 wFAIvMJAKQM9Sak+cK7nqyLdDDtJp5TXE//R4YzBoOEbGU1YTNFBQzzXEU8VoJCVNMiGTY7tITC6B MuKfUsYg==; Received: from fllv0015.ext.ti.com ([198.47.19.141]) by casper.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kqGxj-0006n6-Ue for linux-arm-kernel@lists.infradead.org; Fri, 18 Dec 2020 14:42:35 +0000 Received: from fllv0035.itg.ti.com ([10.64.41.0]) by fllv0015.ext.ti.com (8.15.2/8.15.2) with ESMTP id 0BIEgJ1h002175; Fri, 18 Dec 2020 08:42:19 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1608302539; bh=pTnSOVQlYaLLFPXX46y4VH9Zff6M5493tQ8KFZNlnPg=; h=Subject:To:CC:References:From:Date:In-Reply-To; b=qVoAcJrFpHv8UTLXJKvQVTwSvNJ8ZEnkeV7DBTCkURzuONJJ6bdsu7HivHuSkK4uZ rCK+HZSjzBIG4mlmB6a+4y+SMxztzzM9J38Oqaf0i/GXQ5uULFPBjYrK63pAiC3ygn lNtfC3xxZpPYoxzBWgqwwMBSjjYLM6IeAMvwXP4k= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 0BIEgJQ7111684 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Fri, 18 Dec 2020 08:42:19 -0600 Received: from DFLE102.ent.ti.com (10.64.6.23) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3; Fri, 18 Dec 2020 08:42:18 -0600 Received: from fllv0040.itg.ti.com (10.64.41.20) by DFLE102.ent.ti.com (10.64.6.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1979.3 via Frontend Transport; Fri, 18 Dec 2020 08:42:18 -0600 Received: from [10.250.235.36] (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0040.itg.ti.com (8.15.2/8.15.2) with ESMTP id 0BIEgEl9113653; Fri, 18 Dec 2020 08:42:15 -0600 Subject: Re: [PATCH v5] PCI: cadence: Retrain Link to work around Gen2 training defect. To: Rob Herring References: <20201215070009.27937-1-kishon@ti.com> <1ec78477-dadc-cbef-406f-568f44b6c62d@ti.com> From: Kishon Vijay Abraham I Message-ID: <96ca64cb-ec3a-bb83-2de3-775034ba844b@ti.com> Date: Fri, 18 Dec 2020 20:12:13 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-US X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201218_144232_333205_F69DC006 X-CRM114-Status: GOOD ( 29.49 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Milind Parab , Nadeem Athani , Parshuram Raju Thombare , PCI , "linux-kernel@vger.kernel.org" , Tom Joseph , Swapnil Kashinath Jakhade , Bjorn Helgaas , linux-omap , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Rob, On 16/12/20 10:31 pm, Rob Herring wrote: > On Wed, Dec 16, 2020 at 9:01 AM Kishon Vijay Abraham I wrote: >> >> Hi Rob, >> >> On 15/12/20 9:23 pm, Rob Herring wrote: >>> On Tue, Dec 15, 2020 at 1:00 AM Kishon Vijay Abraham I wrote: >>>> >>>> From: Nadeem Athani >>>> >>>> Cadence controller will not initiate autonomous speed change if strapped as >>>> Gen2. The Retrain Link bit is set as quirk to enable this speed change. >>>> >>>> Signed-off-by: Nadeem Athani >>>> [kishon@ti.com: Enable the workaround for TI's J721E SoC] >>>> Signed-off-by: Kishon Vijay Abraham I >>>> --- >>>> Hi Lorenzo, >>>> The previous version of the patch can be found at [1]. >>>> I slightly re-worked the patch from Nadeem >>>> *) Removed additional Link Up Check >>>> *) Removed quirk from pcie-cadence-plat.c >>>> *) Also removed additional compatible >>>> "cdns,cdns-pcie-host-quirk-retrain" added in that series >>>> *) Enabled the quirk for J721E >>>> [1] -> http://lore.kernel.org/r/20201211144236.3825-1-nadeem@cadence.com >>>> >>>> drivers/pci/controller/cadence/pci-j721e.c | 3 + >>>> .../controller/cadence/pcie-cadence-host.c | 67 ++++++++++++++----- >>>> drivers/pci/controller/cadence/pcie-cadence.h | 11 ++- >>>> 3 files changed, 62 insertions(+), 19 deletions(-) >>>> >>>> diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c >>>> index dac1ac8a7615..baf729850cb1 100644 >>>> --- a/drivers/pci/controller/cadence/pci-j721e.c >>>> +++ b/drivers/pci/controller/cadence/pci-j721e.c >>>> @@ -64,6 +64,7 @@ enum j721e_pcie_mode { >>>> >>>> struct j721e_pcie_data { >>>> enum j721e_pcie_mode mode; >>>> + bool quirk_retrain_flag; >>>> }; >>>> >>>> static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) >>>> @@ -280,6 +281,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = { >>>> >>>> static const struct j721e_pcie_data j721e_pcie_rc_data = { >>>> .mode = PCI_MODE_RC, >>>> + .quirk_retrain_flag = true, >>>> }; >>>> >>>> static const struct j721e_pcie_data j721e_pcie_ep_data = { >>>> @@ -388,6 +390,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) >>>> >>>> bridge->ops = &cdns_ti_pcie_host_ops; >>>> rc = pci_host_bridge_priv(bridge); >>>> + rc->quirk_retrain_flag = data->quirk_retrain_flag; >>>> >>>> cdns_pcie = &rc->pcie; >>>> cdns_pcie->dev = dev; >>>> diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c >>>> index 811c1cb2e8de..773c0d1137ed 100644 >>>> --- a/drivers/pci/controller/cadence/pcie-cadence-host.c >>>> +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c >>>> @@ -77,6 +77,50 @@ static struct pci_ops cdns_pcie_host_ops = { >>>> .write = pci_generic_config_write, >>>> }; >>>> >>>> +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) >>>> +{ >>>> + struct device *dev = pcie->dev; >>>> + int retries; >>>> + >>>> + /* Check if the link is up or not */ >>>> + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { >>>> + if (cdns_pcie_link_up(pcie)) { >>>> + dev_info(dev, "Link up\n"); >>>> + return 0; >>>> + } >>>> + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); >>>> + } >>>> + >>>> + return -ETIMEDOUT; >>>> +} >>>> + >>>> +static void cdns_pcie_retrain(struct cdns_pcie *pcie) >>>> +{ >>>> + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; >>>> + u16 lnk_stat, lnk_ctl; >>>> + >>>> + /* >>>> + * Set retrain bit if current speed is 2.5 GB/s, >>>> + * but the PCIe root port support is > 2.5 GB/s. >>> >>> If you don't have the retrain quirk, wouldn't this condition never >>> happen and then the function is just a nop? So this could just be >>> called unconditionally. >> >> Yeah, but only for the quirk we have to retrain to go to GEN2 speed >> mode. Else the HW will automatically retrain and go to GEN2. > > Again, so you don't need a flag for this. Comparing the speed is > enough. IOW, all you need is: > > if (current speed < advertised speed) > do retrain > > The question is the condition ever true and you don't want to do a > retrain? I could see higher speeds being unstable or something, but For all GEN1 cards there will be re-train (since the Cadence IP RC is GEN2 or more say). This is going to be true for older Cadence IPs and newer Cadence IPs (where Cadence has enabled HW re-training). The quirk will prevent SW re-training for newer Cadence IPs when a GEN1 card is connected. > then 'advertised speed' would be lowered in that case (to prevent auto > retraining, right?) and the condition would be false. I don't think the value in PCI_EXP_LNKCAP will change for unstable links. But yeah it'll fall back to GEN1 based on link training and if the link is unstable it'll again fall back to GEN1 on link RE-training. Thanks, Kishon _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel