From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-1.1 required=3.0 tests=DKIM_SIGNED,DKIM_VALID, DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI,SPF_PASS, URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69FF7C43387 for ; Mon, 14 Jan 2019 12:57:02 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 393B520657 for ; Mon, 14 Jan 2019 12:57:02 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=linaro.org header.i=@linaro.org header.b="g8Uogyfy" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726629AbfANM5A (ORCPT ); Mon, 14 Jan 2019 07:57:00 -0500 Received: from mail-wm1-f68.google.com ([209.85.128.68]:53940 "EHLO mail-wm1-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726449AbfANM47 (ORCPT ); Mon, 14 Jan 2019 07:56:59 -0500 Received: by mail-wm1-f68.google.com with SMTP id d15so8793178wmb.3 for ; Mon, 14 Jan 2019 04:56:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=subject:to:cc:references:from:message-id:date:user-agent :mime-version:in-reply-to:content-language:content-transfer-encoding; bh=eE6TJ5VZ3Nk1FjdARea1smiBFbzx1XYTfg4oJ2JGHJs=; b=g8UogyfyF0r7CuNlezSUf9iYT+RPRjoDO3uSz6mkbnuX//PjptXFIYAVK7rVeOrQ24 5nMTLDJRVxI34R3QTHgPQHZe/r5rYJ1EVouM7l+ZQGaIU2hq9N1IG2uiUdOTLV/EQ0yI RKztBsreD1gDWBPCG0c+aPZIToZ0LEDFqzkGc= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:to:cc:references:from:message-id:date :user-agent:mime-version:in-reply-to:content-language :content-transfer-encoding; bh=eE6TJ5VZ3Nk1FjdARea1smiBFbzx1XYTfg4oJ2JGHJs=; b=X986XT7g23AiitOsJCSYa7y7Sw1YzIHw/9IWG61geEV17cFpqXgcGWs7yusKIphvUp mqi4pSzqS0t75uOTVKFz3JGHSsET1IqDEYvqlvrSMyocdeymzEt+HSsQ84LkPY3KMgo3 3mAtQ478x8y6x1thQYFxHnfVwZAb0cCT0OCE4K6SAbVQueO+HU5p/EiZJJiLVJNy2YLk ZhuOU+2WZ4xHS3WKGsrF6hSjctUOUH9+rOQaq2UsBLCkyAksu33ONJ7KxwqLnrAn0pvJ F34tYj5xUoqHhC/jE/pZ1Xjk7qwUGVPy49C17w6w/uqa3k2o+7239jazwYvgsAyqjiTR 7ClQ== X-Gm-Message-State: AJcUukeXLSRVZaMdrf7uzeH6hvcYfbBT8es3QJZBTX411vkWHiVVuQrC aRmi2PKxk8DWHYa/qkdsRlVtcQ== X-Google-Smtp-Source: ALg8bN5NhSGY+TVdXYyzaakXfLtjuIvc/XiBQFmC7Emp99x4wNII47joUaHwiYlnjHKyGw4Iw3Eozg== X-Received: by 2002:a1c:834c:: with SMTP id f73mr11802641wmd.126.1547470617138; Mon, 14 Jan 2019 04:56:57 -0800 (PST) Received: from [192.168.0.41] (45.70.136.77.rev.sfr.net. [77.136.70.45]) by smtp.googlemail.com with ESMTPSA id 129sm45849167wmd.18.2019.01.14.04.56.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jan 2019 04:56:56 -0800 (PST) Subject: Re: [PATCH v3 0/2] Allwinner A64 timer workaround To: Samuel Holland , Catalin Marinas , Will Deacon , Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , Thomas Gleixner , Marc Zyngier Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com References: <20190113021719.46457-1-samuel@sholland.org> From: Daniel Lezcano Message-ID: <9738319a-4154-62be-2325-2873dfb326dc@linaro.org> Date: Mon, 14 Jan 2019 13:56:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20190113021719.46457-1-samuel@sholland.org> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 13/01/2019 03:17, Samuel Holland wrote: > This is the third version of a patch series to fix system clock jumps > and other timer instability on the Allwinner A64 SoC. It has now been > tested for a week, and I've received no reports of date jumps with this > version. So this is, as far as I can tell, a complete workaround. > > See the commit messages for a detailed description of the issue, but the > summary is that, when a high counter bit rolls over, indeterminance in > the low bits causes CNTPCT/CNTVCT and their respective TVAL registers to > jump forward or backward. Backward jumps (or the next read after forward > jumps) are sometimes seen by the kernel and interpreted as the timer > wrapping around after 2^56 cycles. This causes the system clock to jump > forward approximately 91 years. > > changes since v2; > - Reduced workaround threshold from 11 to 10 bits based on reports from > other hardare and the U-Boot version of this workaround > - Added TVAL handling based on Marc's suggestion > - Added erratum documentation and renamed symbols to match > - Added Maxime's Acked-by > > changes since v1: > - Add an iteration limit like most other arch timer workarounds > - Added Andre's Tested-by > > Samuel Holland (2): > arm64: arch_timer: Workaround for Allwinner A64 timer instability > arm64: dts: allwinner: a64: Enable A64 timer workaround > > Documentation/arm64/silicon-errata.txt | 2 + > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + > drivers/clocksource/Kconfig | 10 ++++ > drivers/clocksource/arm_arch_timer.c | 55 +++++++++++++++++++ > 4 files changed, 68 insertions(+) > Applied. Took the opportunity to add the stable@ tag. Thanks -- Daniel -- Linaro.org │ Open source software for ARM SoCs Follow Linaro: Facebook | Twitter | Blog From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Lezcano Subject: Re: [PATCH v3 0/2] Allwinner A64 timer workaround Date: Mon, 14 Jan 2019 13:56:55 +0100 Message-ID: <9738319a-4154-62be-2325-2873dfb326dc@linaro.org> References: <20190113021719.46457-1-samuel@sholland.org> Reply-To: daniel.lezcano-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Return-path: Sender: linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org In-Reply-To: <20190113021719.46457-1-samuel-RkNLwX/CsU9g9hUCZPvPmw@public.gmane.org> Content-Language: en-US List-Post: , List-Help: , List-Archive: , List-Unsubscribe: , To: Samuel Holland , Catalin Marinas , Will Deacon , Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , Thomas Gleixner , Marc Zyngier Cc: devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org List-Id: devicetree@vger.kernel.org On 13/01/2019 03:17, Samuel Holland wrote: > This is the third version of a patch series to fix system clock jumps > and other timer instability on the Allwinner A64 SoC. It has now been > tested for a week, and I've received no reports of date jumps with this > version. So this is, as far as I can tell, a complete workaround. >=20 > See the commit messages for a detailed description of the issue, but the > summary is that, when a high counter bit rolls over, indeterminance in > the low bits causes CNTPCT/CNTVCT and their respective TVAL registers to > jump forward or backward. Backward jumps (or the next read after forward > jumps) are sometimes seen by the kernel and interpreted as the timer > wrapping around after 2^56 cycles. This causes the system clock to jump > forward approximately 91 years. >=20 > changes since v2; > - Reduced workaround threshold from 11 to 10 bits based on reports from > other hardare and the U-Boot version of this workaround > - Added TVAL handling based on Marc's suggestion > - Added erratum documentation and renamed symbols to match > - Added Maxime's Acked-by >=20 > changes since v1: > - Add an iteration limit like most other arch timer workarounds > - Added Andre's Tested-by >=20 > Samuel Holland (2): > arm64: arch_timer: Workaround for Allwinner A64 timer instability > arm64: dts: allwinner: a64: Enable A64 timer workaround >=20 > Documentation/arm64/silicon-errata.txt | 2 + > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 + > drivers/clocksource/Kconfig | 10 ++++ > drivers/clocksource/arm_arch_timer.c | 55 +++++++++++++++++++ > 4 files changed, 68 insertions(+) >=20 Applied. Took the opportunity to add the stable@ tag. Thanks -- Daniel --=20 Linaro.org =E2=94=82 Open source software for ARM= SoCs Follow Linaro: Facebook | Twitter | Blog --=20 You received this message because you are subscribed to the Google Groups "= linux-sunxi" group. To unsubscribe from this group and stop receiving emails from it, send an e= mail to linux-sunxi+unsubscribe-/JYPxA39Uh5TLH3MbocFF+G/Ez6ZCGd0@public.gmane.org For more options, visit https://groups.google.com/d/optout. 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[77.136.70.45]) by smtp.googlemail.com with ESMTPSA id 129sm45849167wmd.18.2019.01.14.04.56.55 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 14 Jan 2019 04:56:56 -0800 (PST) Subject: Re: [PATCH v3 0/2] Allwinner A64 timer workaround To: Samuel Holland , Catalin Marinas , Will Deacon , Maxime Ripard , Chen-Yu Tsai , Rob Herring , Mark Rutland , Thomas Gleixner , Marc Zyngier References: <20190113021719.46457-1-samuel@sholland.org> From: Daniel Lezcano Message-ID: <9738319a-4154-62be-2325-2873dfb326dc@linaro.org> Date: Mon, 14 Jan 2019 13:56:55 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.2.1 MIME-Version: 1.0 In-Reply-To: <20190113021719.46457-1-samuel@sholland.org> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190114_045700_907072_3EC942D7 X-CRM114-Status: GOOD ( 20.51 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-sunxi@googlegroups.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org T24gMTMvMDEvMjAxOSAwMzoxNywgU2FtdWVsIEhvbGxhbmQgd3JvdGU6Cj4gVGhpcyBpcyB0aGUg dGhpcmQgdmVyc2lvbiBvZiBhIHBhdGNoIHNlcmllcyB0byBmaXggc3lzdGVtIGNsb2NrIGp1bXBz Cj4gYW5kIG90aGVyIHRpbWVyIGluc3RhYmlsaXR5IG9uIHRoZSBBbGx3aW5uZXIgQTY0IFNvQy4g SXQgaGFzIG5vdyBiZWVuCj4gdGVzdGVkIGZvciBhIHdlZWssIGFuZCBJJ3ZlIHJlY2VpdmVkIG5v IHJlcG9ydHMgb2YgZGF0ZSBqdW1wcyB3aXRoIHRoaXMKPiB2ZXJzaW9uLiBTbyB0aGlzIGlzLCBh cyBmYXIgYXMgSSBjYW4gdGVsbCwgYSBjb21wbGV0ZSB3b3JrYXJvdW5kLgo+IAo+IFNlZSB0aGUg Y29tbWl0IG1lc3NhZ2VzIGZvciBhIGRldGFpbGVkIGRlc2NyaXB0aW9uIG9mIHRoZSBpc3N1ZSwg YnV0IHRoZQo+IHN1bW1hcnkgaXMgdGhhdCwgd2hlbiBhIGhpZ2ggY291bnRlciBiaXQgcm9sbHMg b3ZlciwgaW5kZXRlcm1pbmFuY2UgaW4KPiB0aGUgbG93IGJpdHMgY2F1c2VzIENOVFBDVC9DTlRW Q1QgYW5kIHRoZWlyIHJlc3BlY3RpdmUgVFZBTCByZWdpc3RlcnMgdG8KPiBqdW1wIGZvcndhcmQg b3IgYmFja3dhcmQuIEJhY2t3YXJkIGp1bXBzIChvciB0aGUgbmV4dCByZWFkIGFmdGVyIGZvcndh cmQKPiBqdW1wcykgYXJlIHNvbWV0aW1lcyBzZWVuIGJ5IHRoZSBrZXJuZWwgYW5kIGludGVycHJl dGVkIGFzIHRoZSB0aW1lcgo+IHdyYXBwaW5nIGFyb3VuZCBhZnRlciAyXjU2IGN5Y2xlcy4gVGhp cyBjYXVzZXMgdGhlIHN5c3RlbSBjbG9jayB0byBqdW1wCj4gZm9yd2FyZCBhcHByb3hpbWF0ZWx5 IDkxIHllYXJzLgo+IAo+IGNoYW5nZXMgc2luY2UgdjI7Cj4gLSBSZWR1Y2VkIHdvcmthcm91bmQg dGhyZXNob2xkIGZyb20gMTEgdG8gMTAgYml0cyBiYXNlZCBvbiByZXBvcnRzIGZyb20KPiAgIG90 aGVyIGhhcmRhcmUgYW5kIHRoZSBVLUJvb3QgdmVyc2lvbiBvZiB0aGlzIHdvcmthcm91bmQKPiAt IEFkZGVkIFRWQUwgaGFuZGxpbmcgYmFzZWQgb24gTWFyYydzIHN1Z2dlc3Rpb24KPiAtIEFkZGVk IGVycmF0dW0gZG9jdW1lbnRhdGlvbiBhbmQgcmVuYW1lZCBzeW1ib2xzIHRvIG1hdGNoCj4gLSBB ZGRlZCBNYXhpbWUncyBBY2tlZC1ieQo+IAo+IGNoYW5nZXMgc2luY2UgdjE6Cj4gLSBBZGQgYW4g aXRlcmF0aW9uIGxpbWl0IGxpa2UgbW9zdCBvdGhlciBhcmNoIHRpbWVyIHdvcmthcm91bmRzCj4g LSBBZGRlZCBBbmRyZSdzIFRlc3RlZC1ieQo+IAo+IFNhbXVlbCBIb2xsYW5kICgyKToKPiAgIGFy bTY0OiBhcmNoX3RpbWVyOiBXb3JrYXJvdW5kIGZvciBBbGx3aW5uZXIgQTY0IHRpbWVyIGluc3Rh YmlsaXR5Cj4gICBhcm02NDogZHRzOiBhbGx3aW5uZXI6IGE2NDogRW5hYmxlIEE2NCB0aW1lciB3 b3JrYXJvdW5kCj4gCj4gIERvY3VtZW50YXRpb24vYXJtNjQvc2lsaWNvbi1lcnJhdGEudHh0ICAg ICAgICB8ICAyICsKPiAgYXJjaC9hcm02NC9ib290L2R0cy9hbGx3aW5uZXIvc3VuNTBpLWE2NC5k dHNpIHwgIDEgKwo+ICBkcml2ZXJzL2Nsb2Nrc291cmNlL0tjb25maWcgICAgICAgICAgICAgICAg ICAgfCAxMCArKysrCj4gIGRyaXZlcnMvY2xvY2tzb3VyY2UvYXJtX2FyY2hfdGltZXIuYyAgICAg ICAgICB8IDU1ICsrKysrKysrKysrKysrKysrKysKPiAgNCBmaWxlcyBjaGFuZ2VkLCA2OCBpbnNl cnRpb25zKCspCj4gCgpBcHBsaWVkLiBUb29rIHRoZSBvcHBvcnR1bml0eSB0byBhZGQgdGhlIHN0 YWJsZUAgdGFnLgoKVGhhbmtzCgogIC0tIERhbmllbAoKCi0tIAogPGh0dHA6Ly93d3cubGluYXJv Lm9yZy8+IExpbmFyby5vcmcg4pSCIE9wZW4gc291cmNlIHNvZnR3YXJlIGZvciBBUk0gU29DcwoK Rm9sbG93IExpbmFybzogIDxodHRwOi8vd3d3LmZhY2Vib29rLmNvbS9wYWdlcy9MaW5hcm8+IEZh Y2Vib29rIHwKPGh0dHA6Ly90d2l0dGVyLmNvbS8jIS9saW5hcm9vcmc+IFR3aXR0ZXIgfAo8aHR0 cDovL3d3dy5saW5hcm8ub3JnL2xpbmFyby1ibG9nLz4gQmxvZwoKCl9fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fCmxpbnV4LWFybS1rZXJuZWwgbWFpbGluZyBs aXN0CmxpbnV4LWFybS1rZXJuZWxAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5m cmFkZWFkLm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LWFybS1rZXJuZWwK