From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id EDCC6C433F5 for ; Fri, 1 Oct 2021 04:34:32 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C49D261A38 for ; Fri, 1 Oct 2021 04:34:32 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1351616AbhJAEgO (ORCPT ); Fri, 1 Oct 2021 00:36:14 -0400 Received: from foss.arm.com ([217.140.110.172]:34524 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235967AbhJAEgN (ORCPT ); Fri, 1 Oct 2021 00:36:13 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58560106F; Thu, 30 Sep 2021 21:34:29 -0700 (PDT) Received: from [10.163.74.5] (unknown [10.163.74.5]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 410203F70D; Thu, 30 Sep 2021 21:34:24 -0700 (PDT) Subject: Re: [PATCH v2 10/17] arm64: Enable workaround for TRBE overwrite in FILL mode To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-11-suzuki.poulose@arm.com> <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> <4bc00aff-0562-bafd-b31a-d7f9af6651fa@arm.com> From: Anshuman Khandual Message-ID: <9e76e7a8-3cbe-62c2-4cd6-130b3e3784c5@arm.com> Date: Fri, 1 Oct 2021 10:05:32 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <4bc00aff-0562-bafd-b31a-d7f9af6651fa@arm.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 9/22/21 1:41 PM, Suzuki K Poulose wrote: > On 22/09/2021 08:23, Anshuman Khandual wrote: >> >> >> On 9/21/21 7:11 PM, Suzuki K Poulose wrote: >>> Now that we have the work around implmented in the TRBE >>> driver, add the Kconfig entries and document the errata. >>> >>> Cc: Mark Rutland >>> Cc: Will Deacon >>> Cc: Catalin Marinas >>> Cc: Anshuman Khandual >>> Cc: Mathieu Poirier >>> Cc: Mike Leach >>> Cc: Leo Yan >>> Signed-off-by: Suzuki K Poulose >>> --- >>>   Documentation/arm64/silicon-errata.rst |  4 +++ >>>   arch/arm64/Kconfig                     | 39 ++++++++++++++++++++++++++ >>>   2 files changed, 43 insertions(+) >>> >>> diff --git a/Documentation/arm64/silicon-errata.rst b/Documentation/arm64/silicon-errata.rst >>> index d410a47ffa57..2f99229d993c 100644 >>> --- a/Documentation/arm64/silicon-errata.rst >>> +++ b/Documentation/arm64/silicon-errata.rst >>> @@ -92,12 +92,16 @@ stable kernels. >>>   +----------------+-----------------+-----------------+-----------------------------+ >>>   | ARM            | Cortex-A77      | #1508412        | ARM64_ERRATUM_1508412       | >>>   +----------------+-----------------+-----------------+-----------------------------+ >>> +| ARM            | Cortex-A710     | #2119858        | ARM64_ERRATUM_2119858       | >>> ++----------------+-----------------+-----------------+-----------------------------+ >>>   | ARM            | Neoverse-N1     | #1188873,1418040| ARM64_ERRATUM_1418040       | >>>   +----------------+-----------------+-----------------+-----------------------------+ >>>   | ARM            | Neoverse-N1     | #1349291        | N/A                         | >>>   +----------------+-----------------+-----------------+-----------------------------+ >>>   | ARM            | Neoverse-N1     | #1542419        | ARM64_ERRATUM_1542419       | >>>   +----------------+-----------------+-----------------+-----------------------------+ >>> +| ARM            | Neoverse-N2     | #2139208        | ARM64_ERRATUM_2139208       | >>> ++----------------+-----------------+-----------------+-----------------------------+ >>>   | ARM            | MMU-500         | #841119,826419  | N/A                         | >>>   +----------------+-----------------+-----------------+-----------------------------+ >>>   +----------------+-----------------+-----------------+-----------------------------+ >>> diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig >>> index 077f2ec4eeb2..eac4030322df 100644 >>> --- a/arch/arm64/Kconfig >>> +++ b/arch/arm64/Kconfig >>> @@ -666,6 +666,45 @@ config ARM64_ERRATUM_1508412 >>>           If unsure, say Y. >>>   +config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>> +    bool >>> + >>> +config ARM64_ERRATUM_2119858 >>> +    bool "Cortex-A710: 2119858: workaround TRBE overwriting trace data in FILL mode" >>> +    default y >>> +    depends on CORESIGHT_TRBE >>> +    select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>> +    help >>> +      This option adds the workaround for ARM Cortex-A710 erratum 2119858. >>> + >>> +      Affected Cortex-A710 cores could overwrite upto 3 cache lines of trace >>> +      data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in >>> +      the event of a WRAP event. >>> + >>> +      Work around the issue by always making sure we move the TRBPTR_EL1 by >>> +      256bytes before enabling the buffer and filling the first 256bytes of >>> +      the buffer with ETM ignore packets upon disabling. >>> + >>> +      If unsure, say Y. >>> + >>> +config ARM64_ERRATUM_2139208 >>> +    bool "Neoverse-N2: 2139208: workaround TRBE overwriting trace data in FILL mode" >>> +    default y >>> +    depends on CORESIGHT_TRBE >>> +    select ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE >>> +    help >>> +      This option adds the workaround for ARM Neoverse-N2 erratum 2139208. >>> + >>> +      Affected Neoverse-N2 cores could overwrite upto 3 cache lines of trace >>> +      data at the base of the buffer (ponited by TRBASER_EL1) in FILL mode in >> >> s/ponited/pointed >> >>> +      the event of a WRAP event. >>> + >>> +      Work around the issue by always making sure we move the TRBPTR_EL1 by >>> +      256bytes before enabling the buffer and filling the first 256bytes of >>> +      the buffer with ETM ignore packets upon disabling. >>> + >>> +      If unsure, say Y. >>> + >>>   config CAVIUM_ERRATUM_22375 >>>       bool "Cavium erratum 22375, 24313" >>>       default y >>> >> >> The real errata problem description for both these erratums are exactly >> the same. Rather a more generalized description should be included for >> the ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE, which abstracts out the >> problem and a corresponding solution that is implemented in the driver. >> This should also help us reduce current redundancy. >> > > The issue is what a user wants to see. A user who wants to configure the > kernel specifically for a given CPU (think embedded systems), they would > want to hand pick the errata for the particular CPU. So, moving the help > text to an implicitly selected Kconfig symbol. I would rather keep this > as it is to keep it user friendly. This doesn't affect the code size > anyways. Understood. > > The other option is to remove all the CPU specific Kconfig symbols and > update the "title" to reflect both the CPU/erratum numbers. Hmm, but I guess the current proposal is better instead. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AABCBC433F5 for ; Fri, 1 Oct 2021 04:36:25 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6DF4461A55 for ; Fri, 1 Oct 2021 04:36:25 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 6DF4461A55 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender: Content-Transfer-Encoding:Content-Type:List-Subscribe:List-Help:List-Post: List-Archive:List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date: Message-ID:From:References:Cc:To:Subject:Reply-To:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:List-Owner; bh=7NUgRNu8E1wBHqsOzF41WGWsl55iwv67ipbdc2iZvU4=; b=OTtZnejEuVZZFu8SHutLFWl5EX J0PY+LYCeo1a7+VbTcB2LNZ1WfbHyXZM2lVzK49nM1puQisWr2286CwjkpQ7NlTv3CMnf+OLPYdFl s4khrpG7Q/NeskPNZwVzl4Mdq89aYYcvK9ohXLOJjTZZX8bC20elf2F+1YLMPMS0RsOkPoF0Vx4F/ Oly1P7HTGvmyhY//kjenPQhlBJD44eEmJS/5UpdaxZON2GVMI/LNM5T3XibaOJqGyHr5ijZwlzZA2 dHgVyxM3EGNhANqgt/MzSpPUT9RoXNqR1XM7yDxCqTMnYYCR3eZT8jUqcvEjg8VkyqB1vUUWxKZw8 7sw3uiCQ==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWAFp-00Gbej-DG; Fri, 01 Oct 2021 04:34:37 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mWAFl-00GbeL-M4 for linux-arm-kernel@lists.infradead.org; Fri, 01 Oct 2021 04:34:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 58560106F; Thu, 30 Sep 2021 21:34:29 -0700 (PDT) Received: from [10.163.74.5] (unknown [10.163.74.5]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 410203F70D; Thu, 30 Sep 2021 21:34:24 -0700 (PDT) Subject: Re: [PATCH v2 10/17] arm64: Enable workaround for TRBE overwrite in FILL mode To: Suzuki K Poulose , linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org, maz@kernel.org, catalin.marinas@arm.com, mark.rutland@arm.com, james.morse@arm.com, leo.yan@linaro.org, mike.leach@linaro.org, mathieu.poirier@linaro.org, will@kernel.org, lcherian@marvell.com, coresight@lists.linaro.org References: <20210921134121.2423546-1-suzuki.poulose@arm.com> <20210921134121.2423546-11-suzuki.poulose@arm.com> <8b23470b-da5c-c624-dc98-d30ab7c1be5d@arm.com> <4bc00aff-0562-bafd-b31a-d7f9af6651fa@arm.com> From: Anshuman Khandual Message-ID: <9e76e7a8-3cbe-62c2-4cd6-130b3e3784c5@arm.com> Date: Fri, 1 Oct 2021 10:05:32 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <4bc00aff-0562-bafd-b31a-d7f9af6651fa@arm.com> Content-Language: en-US X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210930_213433_844867_7B2150D9 X-CRM114-Status: GOOD ( 22.88 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org CgpPbiA5LzIyLzIxIDE6NDEgUE0sIFN1enVraSBLIFBvdWxvc2Ugd3JvdGU6Cj4gT24gMjIvMDkv MjAyMSAwODoyMywgQW5zaHVtYW4gS2hhbmR1YWwgd3JvdGU6Cj4+Cj4+Cj4+IE9uIDkvMjEvMjEg NzoxMSBQTSwgU3V6dWtpIEsgUG91bG9zZSB3cm90ZToKPj4+IE5vdyB0aGF0IHdlIGhhdmUgdGhl IHdvcmsgYXJvdW5kIGltcGxtZW50ZWQgaW4gdGhlIFRSQkUKPj4+IGRyaXZlciwgYWRkIHRoZSBL Y29uZmlnIGVudHJpZXMgYW5kIGRvY3VtZW50IHRoZSBlcnJhdGEuCj4+Pgo+Pj4gQ2M6IE1hcmsg UnV0bGFuZCA8bWFyay5ydXRsYW5kQGFybS5jb20+Cj4+PiBDYzogV2lsbCBEZWFjb24gPHdpbGxA a2VybmVsLm9yZz4KPj4+IENjOiBDYXRhbGluIE1hcmluYXMgPGNhdGFsaW4ubWFyaW5hc0Bhcm0u Y29tPgo+Pj4gQ2M6IEFuc2h1bWFuIEtoYW5kdWFsIDxhbnNodW1hbi5raGFuZHVhbEBhcm0uY29t Pgo+Pj4gQ2M6IE1hdGhpZXUgUG9pcmllciA8bWF0aGlldS5wb2lyaWVyQGxpbmFyby5vcmc+Cj4+ PiBDYzogTWlrZSBMZWFjaCA8bWlrZS5sZWFjaEBsaW5hcm8ub3JnPgo+Pj4gQ2M6IExlbyBZYW4g PGxlby55YW5AbGluYXJvLm9yZz4KPj4+IFNpZ25lZC1vZmYtYnk6IFN1enVraSBLIFBvdWxvc2Ug PHN1enVraS5wb3Vsb3NlQGFybS5jb20+Cj4+PiAtLS0KPj4+IMKgIERvY3VtZW50YXRpb24vYXJt NjQvc2lsaWNvbi1lcnJhdGEucnN0IHzCoCA0ICsrKwo+Pj4gwqAgYXJjaC9hcm02NC9LY29uZmln wqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoCB8IDM5ICsrKysrKysrKysr KysrKysrKysrKysrKysrCj4+PiDCoCAyIGZpbGVzIGNoYW5nZWQsIDQzIGluc2VydGlvbnMoKykK Pj4+Cj4+PiBkaWZmIC0tZ2l0IGEvRG9jdW1lbnRhdGlvbi9hcm02NC9zaWxpY29uLWVycmF0YS5y c3QgYi9Eb2N1bWVudGF0aW9uL2FybTY0L3NpbGljb24tZXJyYXRhLnJzdAo+Pj4gaW5kZXggZDQx MGE0N2ZmYTU3Li4yZjk5MjI5ZDk5M2MgMTAwNjQ0Cj4+PiAtLS0gYS9Eb2N1bWVudGF0aW9uL2Fy bTY0L3NpbGljb24tZXJyYXRhLnJzdAo+Pj4gKysrIGIvRG9jdW1lbnRhdGlvbi9hcm02NC9zaWxp Y29uLWVycmF0YS5yc3QKPj4+IEBAIC05MiwxMiArOTIsMTYgQEAgc3RhYmxlIGtlcm5lbHMuCj4+ PiDCoCArLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLS0t LSstLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLSsKPj4+IMKgIHwgQVJNwqDCoMKgwqDCoMKg wqDCoMKgwqDCoCB8IENvcnRleC1BNzfCoMKgwqDCoMKgIHwgIzE1MDg0MTLCoMKgwqDCoMKgwqDC oCB8IEFSTTY0X0VSUkFUVU1fMTUwODQxMsKgwqDCoMKgwqDCoCB8Cj4+PiDCoCArLS0tLS0tLS0t LS0tLS0tLSstLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLSsKPj4+ICt8IEFSTcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgfCBDb3J0 ZXgtQTcxMMKgwqDCoMKgIHwgIzIxMTk4NTjCoMKgwqDCoMKgwqDCoCB8IEFSTTY0X0VSUkFUVU1f MjExOTg1OMKgwqDCoMKgwqDCoCB8Cj4+PiArKy0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0t LS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0rCj4+ PiDCoCB8IEFSTcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgfCBOZW92ZXJzZS1OMcKgwqDCoMKgIHwg IzExODg4NzMsMTQxODA0MHwgQVJNNjRfRVJSQVRVTV8xNDE4MDQwwqDCoMKgwqDCoMKgIHwKPj4+ IMKgICstLS0tLS0tLS0tLS0tLS0tKy0tLS0tLS0tLS0tLS0tLS0tKy0tLS0tLS0tLS0tLS0tLS0t Ky0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tKwo+Pj4gwqAgfCBBUk3CoMKgwqDCoMKgwqDC oMKgwqDCoMKgIHwgTmVvdmVyc2UtTjHCoMKgwqDCoCB8ICMxMzQ5MjkxwqDCoMKgwqDCoMKgwqAg fCBOL0HCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgfAo+ Pj4gwqAgKy0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0tLS0t LS0rLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0rCj4+PiDCoCB8IEFSTcKgwqDCoMKgwqDC oMKgwqDCoMKgwqAgfCBOZW92ZXJzZS1OMcKgwqDCoMKgIHwgIzE1NDI0MTnCoMKgwqDCoMKgwqDC oCB8IEFSTTY0X0VSUkFUVU1fMTU0MjQxOcKgwqDCoMKgwqDCoCB8Cj4+PiDCoCArLS0tLS0tLS0t LS0tLS0tLSstLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0t LS0tLS0tLS0tLS0tLS0tLSsKPj4+ICt8IEFSTcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgfCBOZW92 ZXJzZS1OMsKgwqDCoMKgIHwgIzIxMzkyMDjCoMKgwqDCoMKgwqDCoCB8IEFSTTY0X0VSUkFUVU1f MjEzOTIwOMKgwqDCoMKgwqDCoCB8Cj4+PiArKy0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0t LS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0rCj4+ PiDCoCB8IEFSTcKgwqDCoMKgwqDCoMKgwqDCoMKgwqAgfCBNTVUtNTAwwqDCoMKgwqDCoMKgwqDC oCB8ICM4NDExMTksODI2NDE5wqAgfCBOL0HCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDCoMKgwqDC oMKgwqDCoMKgwqDCoMKgwqAgfAo+Pj4gwqAgKy0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0t LS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0rLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0rCj4+ PiDCoCArLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLS0tLSstLS0tLS0tLS0tLS0tLS0t LSstLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLS0tLSsKPj4+IGRpZmYgLS1naXQgYS9hcmNoL2Fy bTY0L0tjb25maWcgYi9hcmNoL2FybTY0L0tjb25maWcKPj4+IGluZGV4IDA3N2YyZWM0ZWViMi4u ZWFjNDAzMDMyMmRmIDEwMDY0NAo+Pj4gLS0tIGEvYXJjaC9hcm02NC9LY29uZmlnCj4+PiArKysg Yi9hcmNoL2FybTY0L0tjb25maWcKPj4+IEBAIC02NjYsNiArNjY2LDQ1IEBAIGNvbmZpZyBBUk02 NF9FUlJBVFVNXzE1MDg0MTIKPj4+IMKgIMKgwqDCoMKgwqDCoMKgIElmIHVuc3VyZSwgc2F5IFku Cj4+PiDCoCArY29uZmlnIEFSTTY0X1dPUktBUk9VTkRfVFJCRV9PVkVSV1JJVEVfRklMTF9NT0RF Cj4+PiArwqDCoMKgIGJvb2wKPj4+ICsKPj4+ICtjb25maWcgQVJNNjRfRVJSQVRVTV8yMTE5ODU4 Cj4+PiArwqDCoMKgIGJvb2wgIkNvcnRleC1BNzEwOiAyMTE5ODU4OiB3b3JrYXJvdW5kIFRSQkUg b3ZlcndyaXRpbmcgdHJhY2UgZGF0YSBpbiBGSUxMIG1vZGUiCj4+PiArwqDCoMKgIGRlZmF1bHQg eQo+Pj4gK8KgwqDCoCBkZXBlbmRzIG9uIENPUkVTSUdIVF9UUkJFCj4+PiArwqDCoMKgIHNlbGVj dCBBUk02NF9XT1JLQVJPVU5EX1RSQkVfT1ZFUldSSVRFX0ZJTExfTU9ERQo+Pj4gK8KgwqDCoCBo ZWxwCj4+PiArwqDCoMKgwqDCoCBUaGlzIG9wdGlvbiBhZGRzIHRoZSB3b3JrYXJvdW5kIGZvciBB Uk0gQ29ydGV4LUE3MTAgZXJyYXR1bSAyMTE5ODU4Lgo+Pj4gKwo+Pj4gK8KgwqDCoMKgwqAgQWZm ZWN0ZWQgQ29ydGV4LUE3MTAgY29yZXMgY291bGQgb3ZlcndyaXRlIHVwdG8gMyBjYWNoZSBsaW5l cyBvZiB0cmFjZQo+Pj4gK8KgwqDCoMKgwqAgZGF0YSBhdCB0aGUgYmFzZSBvZiB0aGUgYnVmZmVy IChwb25pdGVkIGJ5IFRSQkFTRVJfRUwxKSBpbiBGSUxMIG1vZGUgaW4KPj4+ICvCoMKgwqDCoMKg IHRoZSBldmVudCBvZiBhIFdSQVAgZXZlbnQuCj4+PiArCj4+PiArwqDCoMKgwqDCoCBXb3JrIGFy b3VuZCB0aGUgaXNzdWUgYnkgYWx3YXlzIG1ha2luZyBzdXJlIHdlIG1vdmUgdGhlIFRSQlBUUl9F TDEgYnkKPj4+ICvCoMKgwqDCoMKgIDI1NmJ5dGVzIGJlZm9yZSBlbmFibGluZyB0aGUgYnVmZmVy IGFuZCBmaWxsaW5nIHRoZSBmaXJzdCAyNTZieXRlcyBvZgo+Pj4gK8KgwqDCoMKgwqAgdGhlIGJ1 ZmZlciB3aXRoIEVUTSBpZ25vcmUgcGFja2V0cyB1cG9uIGRpc2FibGluZy4KPj4+ICsKPj4+ICvC oMKgwqDCoMKgIElmIHVuc3VyZSwgc2F5IFkuCj4+PiArCj4+PiArY29uZmlnIEFSTTY0X0VSUkFU VU1fMjEzOTIwOAo+Pj4gK8KgwqDCoCBib29sICJOZW92ZXJzZS1OMjogMjEzOTIwODogd29ya2Fy b3VuZCBUUkJFIG92ZXJ3cml0aW5nIHRyYWNlIGRhdGEgaW4gRklMTCBtb2RlIgo+Pj4gK8KgwqDC oCBkZWZhdWx0IHkKPj4+ICvCoMKgwqAgZGVwZW5kcyBvbiBDT1JFU0lHSFRfVFJCRQo+Pj4gK8Kg wqDCoCBzZWxlY3QgQVJNNjRfV09SS0FST1VORF9UUkJFX09WRVJXUklURV9GSUxMX01PREUKPj4+ ICvCoMKgwqAgaGVscAo+Pj4gK8KgwqDCoMKgwqAgVGhpcyBvcHRpb24gYWRkcyB0aGUgd29ya2Fy b3VuZCBmb3IgQVJNIE5lb3ZlcnNlLU4yIGVycmF0dW0gMjEzOTIwOC4KPj4+ICsKPj4+ICvCoMKg wqDCoMKgIEFmZmVjdGVkIE5lb3ZlcnNlLU4yIGNvcmVzIGNvdWxkIG92ZXJ3cml0ZSB1cHRvIDMg Y2FjaGUgbGluZXMgb2YgdHJhY2UKPj4+ICvCoMKgwqDCoMKgIGRhdGEgYXQgdGhlIGJhc2Ugb2Yg dGhlIGJ1ZmZlciAocG9uaXRlZCBieSBUUkJBU0VSX0VMMSkgaW4gRklMTCBtb2RlIGluCj4+Cj4+ IHMvcG9uaXRlZC9wb2ludGVkCj4+Cj4+PiArwqDCoMKgwqDCoCB0aGUgZXZlbnQgb2YgYSBXUkFQ IGV2ZW50Lgo+Pj4gKwo+Pj4gK8KgwqDCoMKgwqAgV29yayBhcm91bmQgdGhlIGlzc3VlIGJ5IGFs d2F5cyBtYWtpbmcgc3VyZSB3ZSBtb3ZlIHRoZSBUUkJQVFJfRUwxIGJ5Cj4+PiArwqDCoMKgwqDC oCAyNTZieXRlcyBiZWZvcmUgZW5hYmxpbmcgdGhlIGJ1ZmZlciBhbmQgZmlsbGluZyB0aGUgZmly c3QgMjU2Ynl0ZXMgb2YKPj4+ICvCoMKgwqDCoMKgIHRoZSBidWZmZXIgd2l0aCBFVE0gaWdub3Jl IHBhY2tldHMgdXBvbiBkaXNhYmxpbmcuCj4+PiArCj4+PiArwqDCoMKgwqDCoCBJZiB1bnN1cmUs IHNheSBZLgo+Pj4gKwo+Pj4gwqAgY29uZmlnIENBVklVTV9FUlJBVFVNXzIyMzc1Cj4+PiDCoMKg wqDCoMKgIGJvb2wgIkNhdml1bSBlcnJhdHVtIDIyMzc1LCAyNDMxMyIKPj4+IMKgwqDCoMKgwqAg ZGVmYXVsdCB5Cj4+Pgo+Pgo+PiBUaGUgcmVhbCBlcnJhdGEgcHJvYmxlbSBkZXNjcmlwdGlvbiBm b3IgYm90aCB0aGVzZSBlcnJhdHVtcyBhcmUgZXhhY3RseQo+PiB0aGUgc2FtZS4gUmF0aGVyIGEg bW9yZSBnZW5lcmFsaXplZCBkZXNjcmlwdGlvbiBzaG91bGQgYmUgaW5jbHVkZWQgZm9yCj4+IHRo ZSBBUk02NF9XT1JLQVJPVU5EX1RSQkVfT1ZFUldSSVRFX0ZJTExfTU9ERSwgd2hpY2ggYWJzdHJh Y3RzIG91dCB0aGUKPj4gcHJvYmxlbSBhbmQgYSBjb3JyZXNwb25kaW5nIHNvbHV0aW9uIHRoYXQg aXMgaW1wbGVtZW50ZWQgaW4gdGhlIGRyaXZlci4KPj4gVGhpcyBzaG91bGQgYWxzbyBoZWxwIHVz IHJlZHVjZSBjdXJyZW50IHJlZHVuZGFuY3kuCj4+Cj4gCj4gVGhlIGlzc3VlIGlzIHdoYXQgYSB1 c2VyIHdhbnRzIHRvIHNlZS4gQSB1c2VyIHdobyB3YW50cyB0byBjb25maWd1cmUgdGhlCj4ga2Vy bmVsIHNwZWNpZmljYWxseSBmb3IgYSBnaXZlbiBDUFUgKHRoaW5rIGVtYmVkZGVkIHN5c3RlbXMp LCB0aGV5IHdvdWxkCj4gd2FudCB0byBoYW5kIHBpY2sgdGhlIGVycmF0YSBmb3IgdGhlIHBhcnRp Y3VsYXIgQ1BVLiBTbywgbW92aW5nIHRoZSBoZWxwCj4gdGV4dCB0byBhbiBpbXBsaWNpdGx5IHNl bGVjdGVkIEtjb25maWcgc3ltYm9sLiBJIHdvdWxkIHJhdGhlciBrZWVwIHRoaXMKPiBhcyBpdCBp cyB0byBrZWVwIGl0IHVzZXIgZnJpZW5kbHkuIFRoaXMgZG9lc24ndCBhZmZlY3QgdGhlIGNvZGUg c2l6ZQo+IGFueXdheXMuCgpVbmRlcnN0b29kLgoKPiAKPiBUaGUgb3RoZXIgb3B0aW9uIGlzIHRv IHJlbW92ZSBhbGwgdGhlIENQVSBzcGVjaWZpYyBLY29uZmlnIHN5bWJvbHMgYW5kCj4gdXBkYXRl IHRoZSAidGl0bGUiIHRvIHJlZmxlY3QgYm90aCB0aGUgQ1BVL2VycmF0dW0gbnVtYmVycy4KCkht bSwgYnV0IEkgZ3Vlc3MgdGhlIGN1cnJlbnQgcHJvcG9zYWwgaXMgYmV0dGVyIGluc3RlYWQuCgpf X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fXwpsaW51eC1hcm0t a2VybmVsIG1haWxpbmcgbGlzdApsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmcK aHR0cDovL2xpc3RzLmluZnJhZGVhZC5vcmcvbWFpbG1hbi9saXN0aW5mby9saW51eC1hcm0ta2Vy bmVsCg==