From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:32908) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsU03-0004Hp-SP for qemu-devel@nongnu.org; Wed, 13 May 2015 06:34:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1YsTzz-0000py-RS for qemu-devel@nongnu.org; Wed, 13 May 2015 06:34:51 -0400 Received: from szxga03-in.huawei.com ([119.145.14.66]:46292) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1YsTzz-0000n2-5N for qemu-devel@nongnu.org; Wed, 13 May 2015 06:34:47 -0400 From: Shlomo Pongratz Date: Wed, 13 May 2015 10:34:31 +0000 Message-ID: References: <00c901d08990$2763c410$762b4c30$@samsung.com> <034301d08c92$dccf6e80$966e4b80$@samsung.com> <03e001d08caf$d7fcd1a0$87f674e0$@samsung.com> In-Reply-To: <03e001d08caf$d7fcd1a0$87f674e0$@samsung.com> Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v2] Add virt-v3 machine that uses GIC-500 List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Pavel Fedin , "qemu-devel@nongnu.org" > -----Original Message----- > From: Pavel Fedin [mailto:p.fedin@samsung.com] > Sent: Tuesday, 12 May, 2015 3:33 PM > To: Shlomo Pongratz; qemu-devel@nongnu.org > Subject: RE: [PATCH v2] Add virt-v3 machine that uses GIC-500 >=20 > Hello! >=20 > > BTW did you try going beyond 16 cores I had problems with 32 and 64 cor= es. >=20 > Just tried it. Works fine, except qemu takes incredibly long time to sta= rt up > with so many cores. 64 cores took something like 2 minutes. Indeed, looks > like freeze, but if you're patient enough, you'll see it running. I belie= ve it's > interpretation mode flaw. >=20 > Kind regards, > Pavel Fedin > Expert Engineer > Samsung Electronics Research center Russia >=20 Hi Pavel, With your patch I can work up to 16 cores it gets stuck at 24 cores. I have two questions regarding your changes. 1. In fdt_add_timer why you didn't used the 24 bit limit I posed on the irq= flags? Please note that the argument is 32 bits wide an 8 bits are for flag= s. 2. In machvirt_init, I used TYPE_AARCH64_CPU while you reverted it to TYPE_= ARM_CPU, I assume this is because you want to support cortex-a15. Don't you= think It should be according to the cortex type? (BTW you removed cortex-a= 53). Best regards, S.P.