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From: "Limonciello, Mario" <Mario.Limonciello@amd.com>
To: Keith Busch <kbusch@kernel.org>
Cc: Christoph Hellwig <hch@lst.de>,
	Hans de Goede <hdegoede@redhat.com>,
	"Deucher, Alexander" <Alexander.Deucher@amd.com>,
	"Liang, Prike" <Prike.Liang@amd.com>,
	"axboe@fb.com" <axboe@fb.com>,
	"sagi@grimberg.me" <sagi@grimberg.me>,
	"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
	"S-k, Shyam-sundar" <Shyam-sundar.S-k@amd.com>
Subject: RE: [PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3 for s2idle
Date: Tue, 25 May 2021 18:27:52 +0000	[thread overview]
Message-ID: <BYAPR12MB2693CD60B17E4FCEED7DD5FCE2259@BYAPR12MB2693.namprd12.prod.outlook.com> (raw)
In-Reply-To: <20210525174505.GA3704559@dhcp-10-100-145-180.wdc.com>

[AMD Official Use Only]

> > This seems like a gross assumption though that evicting the quirks into a
> > central place that every driver needs to behave the same.  AMD's case is
> > specific to NVME, particularly because APST will be used otherwise.
> 
> I don't think you mean APST. That feature enables controller power state
> autonomy, and we do not messed with that on the driver's suspend path.

Relying upon the drive to go into the appropriate low power state via APST is one
aspect of it, and then ASPM for the PCIe link state.

> 
> We do use the explicit nvme specific host managed power state feature,
> though.
> 
> But I also don't see why this is specific to nvme. Are you saying that
> if a some other protocol device was in the same slot, it would be okay
> to use its protocol specific power settings? That doesn't sound right

Maybe Prike can comment more here, but all of these s2idle designs we're talking
about are mobile designs without external PCIe.  OEMs make the decisions on
what PCIe devices are chosen and how they go into the lowest state. 

_______________________________________________
Linux-nvme mailing list
Linux-nvme@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-nvme

  reply	other threads:[~2021-05-25 18:28 UTC|newest]

Thread overview: 26+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-05-25  2:48 [PATCH] nvme-pci: set some AMD PCIe downstream storage device to D3 for s2idle Prike Liang
2021-05-25  6:21 ` Christoph Hellwig
2021-05-25 12:11   ` Liang, Prike
2021-05-25 12:15     ` Christoph Hellwig
2021-05-25 13:39   ` Deucher, Alexander
2021-05-25 13:54     ` Hans de Goede
2021-05-25 14:06       ` Limonciello, Mario
2021-05-25 14:16         ` Christoph Hellwig
2021-05-25 15:18           ` Limonciello, Mario
2021-05-25 17:45             ` Keith Busch
2021-05-25 18:27               ` Limonciello, Mario [this message]
2021-05-25 19:55                 ` Keith Busch
2021-05-25 20:02                 ` Chaitanya Kulkarni
2021-05-26  8:52             ` Hans de Goede
2021-05-26 13:02               ` Christoph Hellwig
2021-05-26 14:45               ` Keith Busch
2021-05-26 14:55                 ` Rafael J. Wysocki
2021-05-26 17:02                   ` Limonciello, Mario
2021-05-26 17:27                     ` Rafael J. Wysocki
2021-05-26 17:32                       ` Limonciello, Mario
2021-05-26 17:42                       ` Limonciello, Mario
2021-05-25 19:59         ` Keith Busch
2021-05-25 20:09           ` Limonciello, Mario
2021-05-25 20:24             ` Keith Busch
2021-05-25 21:51               ` Limonciello, Mario
2021-05-25 14:09       ` Deucher, Alexander

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