diff for duplicates of <CAA85sZvw1s-8CTCt5H_OjW-Q821LSzQOmJyyGYdKHfsDS2Z29A@mail.gmail.com>
diff --git a/a/1.txt b/N1/1.txt
index 92014b2..191823e 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -2,7 +2,7 @@ On Mon, Dec 14, 2020 at 6:44 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
>
> [+cc Jesse, Tony, David, Jakub, Heiner, lists in case there's an ASPM
> issue with I211 or Realtek NICs. Beginning of thread:
-> https://lore.kernel.org/r/20201024205548.1837770-1-ian.kumlien@gmail.com
+> https://lore.kernel.org/r/20201024205548.1837770-1-ian.kumlien at gmail.com
>
> Short story: Ian has:
>
@@ -22,7 +22,7 @@ On Mon, Dec 14, 2020 at 6:44 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > > "5.4.1.2.2. Exit from the L1 State"
> > > >
> > > > Which makes it clear that each switch is required to initiate a
-> > > > transition within 1μs from receiving it, accumulating this latency and
+> > > > transition within 1?s from receiving it, accumulating this latency and
> > > > then we have to wait for the slowest link along the path before
> > > > entering L0 state from L1.
> > > > ...
@@ -60,7 +60,7 @@ On Mon, Dec 14, 2020 at 6:44 AM Bjorn Helgaas <helgaas@kernel.org> wrote:
> > > not a Link).
> >
> > > The Ports advertise L1 exit latencies of <32us, <32us, <32us,
-> > > <16us. If both Links are in L1 and 03:00.0 initiates L1 exit at T,
+> > > <16us. If both Links are in L1 and 03:00.0 initiates L1 exit@T,
> > > 01:00.0 initiates L1 exit at T + 1. A TLP from 03:00.0 may see up
> > > to 1 + 32 = 33us of L1 exit latency.
> > >
@@ -347,7 +347,7 @@ and then the pcie spec showed it as being correct as well... so...
> > > [1] https://bugzilla.kernel.org/attachment.cgi?id=293047
-> > > [2] https://lore.kernel.org/linux-pci/20201007132808.647589-1-ian.kumlien@gmail.com/
+> > > [2] https://lore.kernel.org/linux-pci/20201007132808.647589-1-ian.kumlien at gmail.com/
> > > [3] https://bugzilla.kernel.org/attachment.cgi?id=292955
> > > [4] https://bugzilla.kernel.org/attachment.cgi?id=292957
> > >
@@ -382,7 +382,7 @@ and then the pcie spec showed it as being correct as well... so...
> > > > + *
> > > > + * PCIe r5.0, sec 5.4.1.2.2 states:
> > > > + * A Switch is required to initiate an L1 exit transition on its
-> > > > + * Upstream Port Link after no more than 1 μs from the beginning of an
+> > > > + * Upstream Port Link after no more than 1 ?s from the beginning of an
> > > > + * L1 exit transition on any of its Downstream Port Links.
> > > > *
> > > > * The exit latencies for L1 substates are not advertised
diff --git a/a/content_digest b/N1/content_digest
index aecdd3e..f50f6a0 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -8,28 +8,13 @@
"From\0Ian Kumlien <ian.kumlien\@gmail.com>\0"
]
[
- "Subject\0Re: [PATCH 1/3] PCI/ASPM: Use the path max in L1 ASPM latency check\0"
+ "Subject\0[Intel-wired-lan] [PATCH 1/3] PCI/ASPM: Use the path max in L1 ASPM latency check\0"
]
[
"Date\0Mon, 14 Dec 2020 10:14:18 +0100\0"
]
[
- "To\0Bjorn Helgaas <helgaas\@kernel.org>\0"
-]
-[
- "Cc\0Kai-Heng Feng <kai.heng.feng\@canonical.com>",
- " linux-pci <linux-pci\@vger.kernel.org>",
- " Alexander Duyck <alexander.duyck\@gmail.com>",
- " Saheed O. Bolarinwa <refactormyself\@gmail.com>",
- " Puranjay Mohan <puranjay12\@gmail.com>",
- " Jesse Brandeburg <jesse.brandeburg\@intel.com>",
- " Tony Nguyen <anthony.l.nguyen\@intel.com>",
- " David S. Miller <davem\@davemloft.net>",
- " Jakub Kicinski <kuba\@kernel.org>",
- " Heiner Kallweit <hkallweit1\@gmail.com>",
- " intel-wired-lan <intel-wired-lan\@lists.osuosl.org>",
- " Linux Kernel Network Developers <netdev\@vger.kernel.org>",
- " linux-kernel\@vger.kernel.org <linux-kernel\@vger.kernel.org>\0"
+ "To\0intel-wired-lan\@osuosl.org\0"
]
[
"\0000:1\0"
@@ -42,7 +27,7 @@
">\n",
"> [+cc Jesse, Tony, David, Jakub, Heiner, lists in case there's an ASPM\n",
"> issue with I211 or Realtek NICs. Beginning of thread:\n",
- "> https://lore.kernel.org/r/20201024205548.1837770-1-ian.kumlien\@gmail.com\n",
+ "> https://lore.kernel.org/r/20201024205548.1837770-1-ian.kumlien at gmail.com\n",
">\n",
"> Short story: Ian has:\n",
">\n",
@@ -62,7 +47,7 @@
"> > > > \"5.4.1.2.2. Exit from the L1 State\"\n",
"> > > >\n",
"> > > > Which makes it clear that each switch is required to initiate a\n",
- "> > > > transition within 1\316\274s from receiving it, accumulating this latency and\n",
+ "> > > > transition within 1?s from receiving it, accumulating this latency and\n",
"> > > > then we have to wait for the slowest link along the path before\n",
"> > > > entering L0 state from L1.\n",
"> > > > ...\n",
@@ -100,7 +85,7 @@
"> > > not a Link).\n",
"> >\n",
"> > > The Ports advertise L1 exit latencies of <32us, <32us, <32us,\n",
- "> > > <16us. If both Links are in L1 and 03:00.0 initiates L1 exit at T,\n",
+ "> > > <16us. If both Links are in L1 and 03:00.0 initiates L1 exit\@T,\n",
"> > > 01:00.0 initiates L1 exit at T + 1. A TLP from 03:00.0 may see up\n",
"> > > to 1 + 32 = 33us of L1 exit latency.\n",
"> > >\n",
@@ -387,7 +372,7 @@
"\n",
"\n",
"> > > [1] https://bugzilla.kernel.org/attachment.cgi?id=293047\n",
- "> > > [2] https://lore.kernel.org/linux-pci/20201007132808.647589-1-ian.kumlien\@gmail.com/\n",
+ "> > > [2] https://lore.kernel.org/linux-pci/20201007132808.647589-1-ian.kumlien at gmail.com/\n",
"> > > [3] https://bugzilla.kernel.org/attachment.cgi?id=292955\n",
"> > > [4] https://bugzilla.kernel.org/attachment.cgi?id=292957\n",
"> > >\n",
@@ -422,7 +407,7 @@
"> > > > + *\n",
"> > > > + * PCIe r5.0, sec 5.4.1.2.2 states:\n",
"> > > > + * A Switch is required to initiate an L1 exit transition on its\n",
- "> > > > + * Upstream Port Link after no more than 1 \316\274s from the beginning of an\n",
+ "> > > > + * Upstream Port Link after no more than 1 ?s from the beginning of an\n",
"> > > > + * L1 exit transition on any of its Downstream Port Links.\n",
"> > > > *\n",
"> > > > * The exit latencies for L1 substates are not advertised\n",
@@ -451,4 +436,4 @@
"> > > >"
]
-ee19b3717b14dd5a392016522ccc871b9deaaa52112c27a1add038c62de9e7e0
+c6d2b4d5cc72b35a0fb193d7986dd5f8ce4c3950cffb22d28b4e163409c72cc5
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