From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A43D6C433DB for ; Tue, 30 Mar 2021 02:58:01 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 5C2A2619AA for ; Tue, 30 Mar 2021 02:58:01 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231139AbhC3C52 (ORCPT ); Mon, 29 Mar 2021 22:57:28 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:37116 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231138AbhC3C5V (ORCPT ); Mon, 29 Mar 2021 22:57:21 -0400 Received: from mail-qt1-x833.google.com (mail-qt1-x833.google.com [IPv6:2607:f8b0:4864:20::833]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 1865EC061764 for ; Mon, 29 Mar 2021 19:57:20 -0700 (PDT) Received: by mail-qt1-x833.google.com with SMTP id c6so10968506qtc.1 for ; Mon, 29 Mar 2021 19:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cxay6FlHRSJBcHnRsAPE6LIZ5EwuFLA1D75XOP/1yw8=; b=Rxyfz1b9FAnZKOn9WInbM1Q9jzMo0+uNBQs9kvY8UIXW/wmArOJB+2SssyFq+lD9Cl OOgZezFD8udfExokzGwpTwuXrLEyI33lrZ+u0SU1gjYN4Npju1XSWspYQ+Gh8Zfl0Cjk cC36+I7Hayxwa0DT+Qk8lZ0JrIQFOGxZ+kJQs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cxay6FlHRSJBcHnRsAPE6LIZ5EwuFLA1D75XOP/1yw8=; b=q0AklCxud94sHQl8QdErixw6qbn8PzLhn6e88ONzJGFMdwOT5aFu/3bk0gsEDS+KOB B3zkmjBhkBhDSMnhvA8H7iomW9isA0Cs2t+B7DIdjIiwRin/3R6wXQ39O0LKtAiw3WQF xaZdRyZ4aWEOWg5gXAS2YB8HWRRCqNA9TCttR11HbAIXtUGeCoMvHjOm6UppT2piDONJ RCEdk9154Rq3sfivofAJMVxWFwVmw3JG0lxNg6lB1ZLD9OJQX8NlV353Z4edtBx2SvLz 9LGyJHpKO5tjKOJsiIU9v6STgVNNceXjdsxt46I5WKrXPVx7YgeoaVrSr6bAh6lBHwIX vbGw== X-Gm-Message-State: AOAM5327nB8mAvjGwK12vg/3EDy3H/v0iTyQH3bSwEFQRSD9vreTdwAl +DK+6vz/MYRc1g0eTzljep6UcXCcxBSTKw== X-Google-Smtp-Source: ABdhPJw3j6k/o5sezMadZf204mZ7D5amCfGxvOjXf21Mn7d+kuToDJER844iS83d9ASV4+7CnJXdIw== X-Received: by 2002:ac8:46c9:: with SMTP id h9mr14107769qto.283.1617073038889; Mon, 29 Mar 2021 19:57:18 -0700 (PDT) Received: from mail-yb1-f172.google.com (mail-yb1-f172.google.com. [209.85.219.172]) by smtp.gmail.com with ESMTPSA id r7sm12279922qtm.88.2021.03.29.19.57.17 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Mar 2021 19:57:17 -0700 (PDT) Received: by mail-yb1-f172.google.com with SMTP id x189so15862754ybg.5 for ; Mon, 29 Mar 2021 19:57:17 -0700 (PDT) X-Received: by 2002:a25:74ca:: with SMTP id p193mr20204173ybc.405.1617073036989; Mon, 29 Mar 2021 19:57:16 -0700 (PDT) MIME-Version: 1.0 References: <20210304155144.1.Ic9c04f960190faad5290738b2a35d73661862735@changeid> <20210304155144.3.I60a7fb23ce4589006bc95c64ab8d15c74b876e68@changeid> In-Reply-To: From: Doug Anderson Date: Mon, 29 Mar 2021 19:57:05 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 3/3] drm/bridge: ti-sn65dsi86: Properly get the EDID, but only if refclk To: Laurent Pinchart Cc: Andrzej Hajda , Neil Armstrong , Jonas Karlman , Jernej Skrabec , Sam Ravnborg , Stephen Boyd , linux-arm-msm , Rob Clark , Daniel Vetter , David Airlie , dri-devel , LKML Content-Type: text/plain; charset="UTF-8" Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org Hi, On Tue, Mar 16, 2021 at 5:44 PM Doug Anderson wrote: > > Hi, > > On Tue, Mar 16, 2021 at 2:46 PM Laurent Pinchart > wrote: > > > > Hi Doug, > > > > On Mon, Mar 15, 2021 at 09:25:37AM -0700, Doug Anderson wrote: > > > On Sat, Mar 13, 2021 at 1:17 PM Laurent Pinchart wrote: > > > > On Thu, Mar 04, 2021 at 03:52:01PM -0800, Douglas Anderson wrote: > > > > > In commit 58074b08c04a ("drm/bridge: ti-sn65dsi86: Read EDID blob over > > > > > DDC") we attempted to make the ti-sn65dsi86 bridge properly read the > > > > > EDID from the panel. That commit kinda worked but it had some serious > > > > > problems. > > > > > > > > > > The problems all stem from the fact that userspace wants to be able to > > > > > read the EDID before it explicitly enables the panel. For eDP panels, > > > > > though, we don't actually power the panel up until the pre-enable > > > > > stage and the pre-enable call happens right before the enable call > > > > > with no way to interject in-between. For eDP panels, you can't read > > > > > the EDID until you power the panel. The result was that > > > > > ti_sn_bridge_connector_get_modes() was always failing to read the EDID > > > > > (falling back to what drm_panel_get_modes() returned) until _after_ > > > > > the EDID was needed. > > > > > > > > > > To make it concrete, on my system I saw this happen: > > > > > 1. We'd attach the bridge. > > > > > 2. Userspace would ask for the EDID (several times). We'd try but fail > > > > > to read the EDID over and over again and fall back to the hardcoded > > > > > modes. > > > > > 3. Userspace would decide on a mode based only on the hardcoded modes. > > > > > 4. Userspace would ask to turn the panel on. > > > > > 5. Userspace would (eventually) check the modes again (in Chrome OS > > > > > this happens on the handoff from the boot splash screen to the > > > > > browser). Now we'd read them properly and, if they were different, > > > > > userspace would request to change the mode. > > > > > > > > > > The fact that userspace would always end up using the hardcoded modes > > > > > at first significantly decreases the benefit of the EDID > > > > > reading. Also: if the modes were even a tiny bit different we'd end up > > > > > doing a wasteful modeset and at boot. > > > > > > > > s/and at/at/ ? > > > > > > Sure, I can correct if/when I respin or it can be corrected when landed. > > > > > > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > > > > index 491c9c4f32d1..af3fb4657af6 100644 > > > > > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > > > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > > > > @@ -16,6 +16,7 @@ > > > > > #include > > > > > #include > > > > > #include > > > > > +#include > > > > > > > > > > #include > > > > > > > > > > @@ -130,6 +131,12 @@ > > > > > * @ln_assign: Value to program to the LN_ASSIGN register. > > > > > * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. > > > > > * > > > > > + * @pre_enabled_early: If true we did an early pre_enable at attach. > > > > > + * @pre_enable_timeout_work: Delayed work to undo the pre_enable from attach > > > > > + * if a normal pre_enable never came. > > > > > > > > Could we simplify this by using the runtime PM autosuspend feature ? The > > > > configuration of the bridge would be moved from pre_enable to the PM > > > > runtime resume handler, the clk_disable_unprepare() call moved from > > > > post_disable to the runtime suspend handler, and the work queue replaced > > > > by usage of pm_runtime_put_autosuspend(). > > > > > > It's an interesting idea but I don't think I can make it work, at > > > least not in a generic enough way. Specifically we can also use this > > > bridge chip as a generic GPIO provider in Linux. When someone asks us > > > to read a GPIO then we have to power the bridge on > > > (pm_runtime_get_sync()) and when someone asks us to configure a GPIO > > > as an output then we actually leave the bridge powered until they stop > > > requesting it as an output. At the moment the only user of this > > > functionality (that I know of) is for the HPD pin on trogdor boards > > > (long story about why we don't use the dedicated HPD) but the API > > > supports using these GPIOs for anything and I've tested that it works. > > > It wouldn't be great to have to keep the panel on in order to access > > > the GPIOs. > > > > The issue you're trying to fix doesn't seem specific to this bridge, so > > handling it in the bridge driver bothers me :-S Is there any way we > > could handle this in the DRM core ? I don't want to see similar > > implementations duplicated in all HDMI/DP bridges. > > Yes, it is true that this problem could affect other drivers. ...and > in full disclosure I think there are other similar workarounds already > present. I haven't personally worked on those chips, but in > ps8640_bridge_get_edid() there is a somewhat similar workaround to > chain a pre-enable (though maybe it's not quite as optimized?). I'm > told that maybe something had to be handled for anx7625 (in > anx7625_get_edid()?) but that definitely doesn't look at all like it's > doing a pre-enable, so maybe things for that bridge just work > differently. > > One thing that makes me hesitant about trying to moving this to the > core is that even in sn65dsi86 there is a case where it won't work. As > I mentioned in the patch I'm not aware of anyone using it in > production, but if someone was using the MIPI clock as input to the > bridge chip instead of a fixed "refclk" then trying to get the EDID > after just "pre-enable" falls over. Said another way: I can say that > with this particular bridge chip, if you're using a fixed refclk, you > can read the EDID after the pre-enable. I don't know if that's always > true with all other bridge chips. > > So I guess in summary: I think I could put my code in the core, but I > don't _think_ I can just make it automatically enabled. > > * In sn65dsi I'd have to only enable it if we have a fixed refclk. > > * Maybe in ps8640 I could just always enable it and replace the > existing code? I'd have to find someone to test. > > * In anx7625 things look totally different. > > Can you give me any advice on how you'd like me to proceed? OK, I've got something that maybe looks better. You can tell me what you think [1]. I did manage to use PM Runtime to avoid some of the complexity and I put that usage in simple-panel. We'll see if I get yelled at for adding more to simple-panel. ;-P [1] https://lore.kernel.org/dri-devel/20210330025345.3980086-1-dianders@chromium.org/ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3F47FC433DB for ; Tue, 30 Mar 2021 02:57:22 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EC1926192B for ; Tue, 30 Mar 2021 02:57:21 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EC1926192B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=chromium.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E7E746E830; Tue, 30 Mar 2021 02:57:20 +0000 (UTC) Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7F5A86E830 for ; Tue, 30 Mar 2021 02:57:20 +0000 (UTC) Received: by mail-qt1-x829.google.com with SMTP id u8so10900555qtq.12 for ; Mon, 29 Mar 2021 19:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=mime-version:references:in-reply-to:from:date:message-id:subject:to :cc; bh=cxay6FlHRSJBcHnRsAPE6LIZ5EwuFLA1D75XOP/1yw8=; b=Rxyfz1b9FAnZKOn9WInbM1Q9jzMo0+uNBQs9kvY8UIXW/wmArOJB+2SssyFq+lD9Cl OOgZezFD8udfExokzGwpTwuXrLEyI33lrZ+u0SU1gjYN4Npju1XSWspYQ+Gh8Zfl0Cjk cC36+I7Hayxwa0DT+Qk8lZ0JrIQFOGxZ+kJQs= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=cxay6FlHRSJBcHnRsAPE6LIZ5EwuFLA1D75XOP/1yw8=; b=eRYTp70qy6N9MNUjJz+vwYWRSvzTritCNWOqCLHt2X1xi4b7Pb3KI+fS1CDxifstOV BbhiGDTKzzxBgDDRjdMZO0Xj4SO7jz09Rm5c4gNwXSFPb9TAU+SANiH9lBGutX9lTe0V bPpgd0NL/q/QoIDs5WEBGWZCjl1HY1M0laz5oNNmA9GeJKyEczXwxqxgXYtQt0lC1eys PhhXEz9z4uWXnPlNZlb8YGnXYnCx2N/UmpknJhzyzeQ7Qw9FyiYJGyOZe4P4dVquPeaS uPi4mlMghuV/YfYex1iLEoNzMIib+Wl/X4IOxvAAs7GVWFmBIApjkMohNKQp/LvmdRcj WWmg== X-Gm-Message-State: AOAM533qsmgjfl9XG1E9G8B6jeCLG9q5ms8+1DcAHPuhBhnUdIXDvRau mjhOpYp1uqDyP3CH53RM5tBUgLxZ1avdcQ== X-Google-Smtp-Source: ABdhPJw5WgHeDqXEY7FaMCli5/rKFKC/Hp9kheA8Jj8X/ns/0JUTqOs8WyqrIyekOcX/pwOP6fzHcQ== X-Received: by 2002:ac8:4718:: with SMTP id f24mr25754452qtp.270.1617073038986; Mon, 29 Mar 2021 19:57:18 -0700 (PDT) Received: from mail-yb1-f178.google.com (mail-yb1-f178.google.com. [209.85.219.178]) by smtp.gmail.com with ESMTPSA id o21sm12270726qtp.72.2021.03.29.19.57.17 for (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 29 Mar 2021 19:57:17 -0700 (PDT) Received: by mail-yb1-f178.google.com with SMTP id a143so15857934ybg.7 for ; Mon, 29 Mar 2021 19:57:17 -0700 (PDT) X-Received: by 2002:a25:74ca:: with SMTP id p193mr20204173ybc.405.1617073036989; Mon, 29 Mar 2021 19:57:16 -0700 (PDT) MIME-Version: 1.0 References: <20210304155144.1.Ic9c04f960190faad5290738b2a35d73661862735@changeid> <20210304155144.3.I60a7fb23ce4589006bc95c64ab8d15c74b876e68@changeid> In-Reply-To: From: Doug Anderson Date: Mon, 29 Mar 2021 19:57:05 -0700 X-Gmail-Original-Message-ID: Message-ID: Subject: Re: [PATCH 3/3] drm/bridge: ti-sn65dsi86: Properly get the EDID, but only if refclk To: Laurent Pinchart X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Clark , Jernej Skrabec , Jonas Karlman , David Airlie , linux-arm-msm , Neil Armstrong , LKML , dri-devel , Stephen Boyd , Andrzej Hajda , Sam Ravnborg Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Hi, On Tue, Mar 16, 2021 at 5:44 PM Doug Anderson wrote: > > Hi, > > On Tue, Mar 16, 2021 at 2:46 PM Laurent Pinchart > wrote: > > > > Hi Doug, > > > > On Mon, Mar 15, 2021 at 09:25:37AM -0700, Doug Anderson wrote: > > > On Sat, Mar 13, 2021 at 1:17 PM Laurent Pinchart wrote: > > > > On Thu, Mar 04, 2021 at 03:52:01PM -0800, Douglas Anderson wrote: > > > > > In commit 58074b08c04a ("drm/bridge: ti-sn65dsi86: Read EDID blob over > > > > > DDC") we attempted to make the ti-sn65dsi86 bridge properly read the > > > > > EDID from the panel. That commit kinda worked but it had some serious > > > > > problems. > > > > > > > > > > The problems all stem from the fact that userspace wants to be able to > > > > > read the EDID before it explicitly enables the panel. For eDP panels, > > > > > though, we don't actually power the panel up until the pre-enable > > > > > stage and the pre-enable call happens right before the enable call > > > > > with no way to interject in-between. For eDP panels, you can't read > > > > > the EDID until you power the panel. The result was that > > > > > ti_sn_bridge_connector_get_modes() was always failing to read the EDID > > > > > (falling back to what drm_panel_get_modes() returned) until _after_ > > > > > the EDID was needed. > > > > > > > > > > To make it concrete, on my system I saw this happen: > > > > > 1. We'd attach the bridge. > > > > > 2. Userspace would ask for the EDID (several times). We'd try but fail > > > > > to read the EDID over and over again and fall back to the hardcoded > > > > > modes. > > > > > 3. Userspace would decide on a mode based only on the hardcoded modes. > > > > > 4. Userspace would ask to turn the panel on. > > > > > 5. Userspace would (eventually) check the modes again (in Chrome OS > > > > > this happens on the handoff from the boot splash screen to the > > > > > browser). Now we'd read them properly and, if they were different, > > > > > userspace would request to change the mode. > > > > > > > > > > The fact that userspace would always end up using the hardcoded modes > > > > > at first significantly decreases the benefit of the EDID > > > > > reading. Also: if the modes were even a tiny bit different we'd end up > > > > > doing a wasteful modeset and at boot. > > > > > > > > s/and at/at/ ? > > > > > > Sure, I can correct if/when I respin or it can be corrected when landed. > > > > > > > > diff --git a/drivers/gpu/drm/bridge/ti-sn65dsi86.c b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > > > > index 491c9c4f32d1..af3fb4657af6 100644 > > > > > --- a/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > > > > +++ b/drivers/gpu/drm/bridge/ti-sn65dsi86.c > > > > > @@ -16,6 +16,7 @@ > > > > > #include > > > > > #include > > > > > #include > > > > > +#include > > > > > > > > > > #include > > > > > > > > > > @@ -130,6 +131,12 @@ > > > > > * @ln_assign: Value to program to the LN_ASSIGN register. > > > > > * @ln_polrs: Value for the 4-bit LN_POLRS field of SN_ENH_FRAME_REG. > > > > > * > > > > > + * @pre_enabled_early: If true we did an early pre_enable at attach. > > > > > + * @pre_enable_timeout_work: Delayed work to undo the pre_enable from attach > > > > > + * if a normal pre_enable never came. > > > > > > > > Could we simplify this by using the runtime PM autosuspend feature ? The > > > > configuration of the bridge would be moved from pre_enable to the PM > > > > runtime resume handler, the clk_disable_unprepare() call moved from > > > > post_disable to the runtime suspend handler, and the work queue replaced > > > > by usage of pm_runtime_put_autosuspend(). > > > > > > It's an interesting idea but I don't think I can make it work, at > > > least not in a generic enough way. Specifically we can also use this > > > bridge chip as a generic GPIO provider in Linux. When someone asks us > > > to read a GPIO then we have to power the bridge on > > > (pm_runtime_get_sync()) and when someone asks us to configure a GPIO > > > as an output then we actually leave the bridge powered until they stop > > > requesting it as an output. At the moment the only user of this > > > functionality (that I know of) is for the HPD pin on trogdor boards > > > (long story about why we don't use the dedicated HPD) but the API > > > supports using these GPIOs for anything and I've tested that it works. > > > It wouldn't be great to have to keep the panel on in order to access > > > the GPIOs. > > > > The issue you're trying to fix doesn't seem specific to this bridge, so > > handling it in the bridge driver bothers me :-S Is there any way we > > could handle this in the DRM core ? I don't want to see similar > > implementations duplicated in all HDMI/DP bridges. > > Yes, it is true that this problem could affect other drivers. ...and > in full disclosure I think there are other similar workarounds already > present. I haven't personally worked on those chips, but in > ps8640_bridge_get_edid() there is a somewhat similar workaround to > chain a pre-enable (though maybe it's not quite as optimized?). I'm > told that maybe something had to be handled for anx7625 (in > anx7625_get_edid()?) but that definitely doesn't look at all like it's > doing a pre-enable, so maybe things for that bridge just work > differently. > > One thing that makes me hesitant about trying to moving this to the > core is that even in sn65dsi86 there is a case where it won't work. As > I mentioned in the patch I'm not aware of anyone using it in > production, but if someone was using the MIPI clock as input to the > bridge chip instead of a fixed "refclk" then trying to get the EDID > after just "pre-enable" falls over. Said another way: I can say that > with this particular bridge chip, if you're using a fixed refclk, you > can read the EDID after the pre-enable. I don't know if that's always > true with all other bridge chips. > > So I guess in summary: I think I could put my code in the core, but I > don't _think_ I can just make it automatically enabled. > > * In sn65dsi I'd have to only enable it if we have a fixed refclk. > > * Maybe in ps8640 I could just always enable it and replace the > existing code? I'd have to find someone to test. > > * In anx7625 things look totally different. > > Can you give me any advice on how you'd like me to proceed? OK, I've got something that maybe looks better. You can tell me what you think [1]. I did manage to use PM Runtime to avoid some of the complexity and I put that usage in simple-panel. We'll see if I get yelled at for adding more to simple-panel. ;-P [1] https://lore.kernel.org/dri-devel/20210330025345.3980086-1-dianders@chromium.org/ _______________________________________________ dri-devel mailing list dri-devel@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/dri-devel