From mboxrd@z Thu Jan  1 00:00:00 1970
From: Bin Meng <bmeng.cn@gmail.com>
Date: Mon, 4 Nov 2019 16:50:38 +0800
Subject: [U-Boot] [PATCH v3 041/108] x86: Reduce mrccache record
	alignment size
In-Reply-To: <20191021033913.220758-41-sjg@chromium.org>
References: <20191021033913.220758-22-sjg@chromium.org>
 <20191021033913.220758-41-sjg@chromium.org>
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On Mon, Oct 21, 2019 at 11:40 AM Simon Glass <sjg@chromium.org> wrote:
>
> At present the records are 4KB in size. This is unnecessarily large when
> the SPI-flash erase size is 256 bytes. Reduce it so it will be more
> efficient with Apollolake's 24-byte variable-data record.
>
> Signed-off-by: Simon Glass <sjg@chromium.org>
> ---
>
> Changes in v3: None
> Changes in v2: None
>
>  arch/x86/include/asm/mrccache.h | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>

Reviewed-by: Bin Meng <bmeng.cn@gmail.com>