From: Peter Maydell <peter.maydell@linaro.org>
To: Jeff Kubascik <jeff.kubascik@dornerworks.com>
Cc: Stewart Hildebrand <Stewart.Hildebrand@dornerworks.com>,
qemu-arm <qemu-arm@nongnu.org>,
QEMU Developers <qemu-devel@nongnu.org>,
Jarvis Roach <Jarvis.Roach@dornerworks.com>
Subject: Re: [PATCH] arm/gicv3: update virtual irq state after IAR register read
Date: Thu, 16 Jan 2020 18:03:53 +0000 [thread overview]
Message-ID: <CAFEAcA-Y5EL5ty_9b1E8OwKEncxsZnyh24stnYVOnUQrrdjsSQ@mail.gmail.com> (raw)
In-Reply-To: <20200113154607.97032-1-jeff.kubascik@dornerworks.com>
On Mon, 13 Jan 2020 at 15:46, Jeff Kubascik
<jeff.kubascik@dornerworks.com> wrote:
>
> The IAR0/IAR1 register is used to acknowledge an interrupt - a read of the
> register activates the highest priority pending interrupt and provides its
> interrupt ID. Activating an interrupt can change the CPU's virtual interrupt
> state - this change makes sure the virtual irq state is updated.
>
> Signed-off-by: Jeff Kubascik <jeff.kubascik@dornerworks.com>
> ---
Applied to target-arm.next, thanks.
-- PMM
prev parent reply other threads:[~2020-01-16 18:05 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-01-13 15:46 [PATCH] arm/gicv3: update virtual irq state after IAR register read Jeff Kubascik
2020-01-13 17:05 ` Philippe Mathieu-Daudé
2020-01-16 18:03 ` Peter Maydell [this message]
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